Native Phy Ip Parameter Settings For Interlaken - Intel Arria 10 User Manual

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15

2.5.5. Native PHY IP Parameter Settings for Interlaken

This section contains the recommended parameter values for this protocol. Refer to
Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter
values.
Table 76. General and Datapath Parameters
Message level for rule violations
Transceiver configuration rules
PMA configuration rules
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Provide separate interface for each channel
Table 77. TX PMA Parameters
TX channel bonding mode
PCS TX channel bonding master
Actual PCS TX channel bonding master
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port
tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable tx_pma_qpipullup port (QPI)
Parameter
Parameter
Value
error
warning
Interlaken
basic
TX / RX Duplex
TX Simplex
RX Simplex
1 to 96
Up to 17.4 Gbps for GX devices
(Depending on Enhanced PCS to PMA interface width
selection)
On / Off
On / Off
On / Off
Value
Not bonded
PMA-only bonding
PMA and PCS bonding
If TX channel bonding mode is set to PMA and PCS
bonding, then:
Auto, 0, 1, 2, 3 through [Number of data channels – 1]
If TX channel bonding mode is set to PMA and PCS
bonding, then:
0, 1, 2, 3 through [Number of data channels – 1]
If TX channel bonding mode is not bonded, then:
1, 2, 4, 8
If TX channel bonding mode is not bonded, then:
1, 2, 3, 4
0
On / Off
On / Off
When Enable tx_pma_div_clkout port is On, then:
Disabled, 1, 2, 33, 40, 66
On / Off
Off
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Intel Arria
continued...
10 Transceiver PHY User Guide
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