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A
S
BOUT THE
ERVER
[1.3.195] GPIO List (Continued)
I
P
#
P
N
TEM
IN
IN
AME
6
AR16
PIRQH_N_GPIO5
7
Y31
TACH2_GPIO6
8
AJ35
TACH3_GPIO7
9
F38
GPIO8
10
L39
OC5_N_GPIO9
IO
P
OWER
PU/PD
R
ECOMMENDATIONS
TYPE
WELL
(
REFERENCE DESIGN
"In Main Power Well.
Muxed with PIRQ[H:E]#.
Defaults to GPI. If not
I
P1V1_SSB
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
"In Main Power Well.
Muxed with TACH[3:2].
Defaults to GPI. If not
I
P1V1_SSB
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
"In Main Power Well.
Muxed with TACH[3:2].
Defaults to GPI. If not
I
P1V1_SSB
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
"In Suspend Power Well.
I
P3V3_AUX
PU
Unmuxed. Defaults to
GPO. "
"In Suspend Power Well.
Muxed with OC5#.
Defaults to OC5#. If not
I
P3V3_AUX
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
V
A
ENDOR
LTERNATE
U
SED
FUNCTION
FUNCTION
)
(D
)
EFAULT
PIRQH_N
GPI
(GPI)
TACH2
GPI
(GPI)
TACH3
GPI
(GPI)
IRQ_CATE
RR_DLY_B
GPI
UF_N
(GPO)
OC5_N
GPI
(GPI)
1-59
N
STATE
ET
NET
AFTER
CONNECT
NAME
RESET
TO
BMC via
level shift
IRQ_IBMC
and pull
_SSB_NM
high
P3V3
up P3V3
I
via
10Kohm
PU to
P3V3 via
BOARD_S
high
10K (NI)
KU2
and PD
via 10K
PU to
P3V3 via
BOARD_R
high
10K and
EVISION0
PD via
10K (NI)
CPU via
GTL/
LVTTL
transla-
IRQ_CAT
tor, D flip
P3V3
ERR_DLY
high
flop, buf-
_AUX
_BUF_N
fer and
pull up
P3V3_A
UX via
4.7Kohm
pull up
PU_USB_
P3V3_A
high
OC5_N
UX via
10Kohm
GPIO L
IST
board
SKU ID
board
revi-
sion ID
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