QUANTA W Mainboard Series S210-MBT2W Technical Manual page 88

A S
BOUT THE ERVER
[1.3.195] GPIO List (Continued)
I P # P N
TEM IN IN AME
25 F34 GPIO24
26 J38 GPIO25
27 F31 GPIO26
28 M35 GPIO27
IO P
OWER
PU/PD R
ECOMMENDATIONS
TYPE WELL
(
REFERENCE DESIGN
"In Suspend Power Well.
Unmuxed. Defaults to
I P3V3_AUX PU GPO. This GPIO is not
cleared by a CF9 reset
event."
"In Suspend Power Well.
O P3V3_AUX PU Unmuxed. Defaults to
GPO. "
"In Suspend Power Well.
O P3V3_AUX PU Unmuxed. Defaults to
GPO. "
"In Deep Sleep Power
Well. Unmuxed. Defaults
O P3V3_AUX PU to GPI. If not used, require
a weak pull-up (8.2kohm to
10kohm) to VccDSW3_3"
V A
ENDOR LTERNATE
U
SED
FUNCTION
FUNCTION
) (D )
EFAULT
GPIO24
GPI
(GPO)
GPIO25
GPO
(GPO)
GPIO26
GPO
(GPO)
GPIO27
GPO
(GPI)
1-63
N
STATE ET
NET
AFTER CONNECT
NAME
RESET TO
connect
to pin2 of
JP3
(RAID
FM_PBG_ Key con-
P3V3
DYN_SKU high nector)
_AUX
_KEY and pull
up
P3V3_A
UX via
750 ohm
JTAG_PB Connect
P3V3
G_PLD_T high to CPLD
_AUX
DI TDI
"1. con-
nect to
pin2 of
J1E7
and
JTAG_PB JTAG_P
P3V3
G_PLD_T high LD_TCK
_AUX
CK via a
475ohm(
empty) 2.
Connect
to CPLD
TCK"
Connect
FP_PWR_ to Front P3V3
high
LED_N Panel via _AUX
a buffer
GPIO L
IST
Upgrad
e KEY
JTAG
Reserv
ed for
JTAG
for
CPLD
on-line
update
Power
LED
control