QUANTA W Mainboard Series S210-MBT2W Technical Manual page 116

A S
BOUT THE ERVER
[1.3.267] S210-MBT2W 12V Power Rail Distribution for UP-M
C TDP(W
ONNE
D
EVICE
)
CTOR
VCCP
120.75
CPU1
VSA_C
17.00
2x4 Pin
PU1
CPU1
P1V8_
P12V2
3.60
CPU1
P1V05_
21.00
CPU1
Total 162.35
Slot6 21.42
2x4 pin
VDDQ_
CPU1
DIMM
P12V3
50.00
CD_CP
B
U0
VDDQ_
DIMM
50.00
EF_CP
U1
Total 121.42
P (A P12V C
EAK
TDC(A)
) TDC(A)
115.00 150.00 14.71
20.00 24.00
2.00 2.00
20.00
14.71+
14.71 1.24=1
5.95
1.79 2.10 1.79
33.33 50.00 4.90
33.33 50.00 4.90
P12V3
A+P12
11.59
V3B>18
A
[1.3.268] Power connector each power rating is 9 A, 2 pin is 18
A; DFQR connector pin derating parameter is 0.85.
OMME
18x0.85=15.3A.
NT
2x2 Power Conn: Power connector rating is 9 A per pin; 2

pin is 18 A; DFQ&R connector pin derating parameter is
85%. So 18x0.85=15.3A.
2x2 Power "Plus" Conn: Power "Plus" connector rating is

12 A per pin; 2 pin is 24 A; DFQ&R connector pin derating
parameter is 85%. So 24x0.85=20.4A.
2x3 Power Conn: Power connector rating is 9 A per pin; 3

pin is 27 A; DFQ&R connector pin derating parameter is
85%. So 27x0.85=23.0A.
2x4 Power Conn: Power connector rating is 9 A per pin; 4

pin is 36 A; DFQ&R connector pin derating parameter is
85%. So 36x0.85=30.6A.
[1.3.269] DC-DC Power Sub-sys-
tem
[1.3.270] This product will utilize high efficiency VRs at a cost
effective price range.
[1.3.271] To reduce losses in Vcore and Vmemory VRs at light
loads, i.e. 10% to 20% of TDC, phase shedding techniques via
the SVID interface can be used. VR12.0 will support phase
shedding.
1-91
DC-DC P S -
OWER UB SYSTEM