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A
S
BOUT THE
ERVER
[1.3.33] Oversubscription of DMI2
[1.3.34] Architecture is aware that the Patsburg DMI2 link will
be oversubscribed when there is max use of IO without the
Gen3 uplink connected. The PBG/CPT team indicated that
they have a bug on their arbitration logic where the PCIe Gen 2
Ports 1 and 5 are the only ones that get a Grant Count value of
4 and the PCIe Gen 2 Ports 2, 3, 4, 6, 7, 8 get Grant Count val-
ues of 1.
[1.3.35] SAS Module
[1.3.36] The S210-MBT2W Server will support the Intel
designed Romley SAS ROC Module in PCIe slot 4. A special
bulkhead for the module will be needed for the "Rack" configu-
ration designed by 3rd party (Kontron).
[1.3.40] Riser IDs
3
3
3
3
D
C
B
A
Riser
SLT2
S
2
OCKET
2
2
2
2
1
1
D
C
B
A
B
A
[1.3.37] Riser Support for 3rd Party
Chassis
[1.3.38] S210-MBT2W can support PCIe I/O risers in slots 2, 5,
and 6. GPIOs on the PCH will need to be used so that different
riser types can be identified according to the following tables.
Slot 2 has two clocks, slot 5 has three clocks, and slot 6 has
three clocks for supporting riser slots. Note: The I/O Riser
Boards for slots 5&6 will need to have pin B31 grounded.
[1.3.39] Riser ID Definition
LAN-
SUS_ST
PHYPC/
AT#/
GPIO12
GPIO61
FM_RISE
FM_RISE
R_ID4
R_ID3
Riser
Riser
Riser Slot
Slot5&6
Slot5 pin
Usage
pin A50
B31 ID2
ID1
ID4 ID3 ID2 ID1
ID0
3
3
3
D
C
x
x
x
1-29
GPIO66
GPIO65
FM_RISE
FM_RISE
R_ID2
R_ID1
Riser
Riser
Slot5&6
Slot2 pin
pin B48
A50 ID1
ID0
S
1
OCKET
3
2
2
2
2
B
A
D
C
B
A
x
SAS M
ODULE
GPIO64
FM_RISE
R_ID0
Riser
Slot2 pin
B48 ID0
1
1
B
A
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