Table of Contents
Advertisement
A
S
BOUT THE
ERVER
[1.3.195] GPIO List (Continued)
I
P
#
P
N
TEM
IN
IN
AME
67
AL15
GPIO66
68
AK15
GPIO67
69
AG34
TACH4_GPIO68
70
Y32
TACH5_GPIO69
71
AF34
TACH6_GPIO70
IO
P
OWER
PU/PD
R
ECOMMENDATIONS
TYPE
WELL
(
REFERENCE DESIGN
"In Core Power Well.
I
P1V1_SSB
NA
Unmuxed. Defaults to
GPO. "
"In Core Power Well.
I
P1V1_SSB
NA
Unmuxed. Defaults to
GPO. "
"In Core Power Well.
Muxed with TACH4.
Defaults to GPI. If not
I
P1V1_SSB
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
"In Core Power Well.
Muxed with TACH5.
Defaults to GPI. If not
I
P1V1_SSB
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
"In Core Power Well.
Muxed with TACH6.
Defaults to GPI. If not
I
P1V1_SSB
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
V
A
ENDOR
LTERNATE
U
SED
FUNCTION
FUNCTION
)
(D
)
EFAULT
GPIO66
GPO
(GPO)
GPIO67
GPO
(GPO)
TACH4
GPI
(GPI)
TACH5
GPI
(GPI)
TACH6
GPI
(GPI)
1-72
N
STATE
ET
NET
AFTER
CONNECT
NAME
RESET
TO
connect
to
Slot5and
FM_RISE
Slot6
high
P3V3
R_ID2
and pull
up P3V3
via
1Kohm
FW_1394
Board
_DISABLE
1394 dis-
P3V3
_N
able pin
PU to
P3V3 via
BOARD_R
high
10K (NI)
P3V3
EVISION1
and PD
via 10K
Connect
to PCIE
"PCIE_SL
slot4 and
OT4_PRE
high
P3V3
PU to
SENT_N"
P3V3 via
10K
Connect
to PCIE
PCIE_SL
slot5 and
OT5_PRE
high
P3V3
PU to
SENT_N
P3V3 via
10K
GPIO L
IST
PCIE
slot6
riser
1394
disable
pin
board
revi-
sion ID
PCIE
slot4
pres-
ent pin
PCIE
slot5
pres-
ent pin
Hide quick links:
Advertisement
Table of Contents
