QUANTA W Mainboard Series S210-MBT2W Technical Manual page 96

A S
BOUT THE ERVER
[1.3.195] GPIO List (Continued)
I P # P N
TEM IN IN AME
SUS_STAT_N_GPIO
62 E36
61
63 C35 SUSCLK_GPIO62
64 B35 SLP_S5_N_GPIO63
65 AL16 GPIO64
66 AK16 GPIO65
IO P
OWER
PU/PD R
ECOMMENDATIONS
TYPE WELL
(
REFERENCE DESIGN
"In Suspend Power Well.
O P3V3_AUX NA Muxed with SUS_STAT#.
Defaults to SUS_STAT#. "
"In Suspend Power Well.
O P3V3_AUX NA Muxed with SUSCLK.
Defaults to SUSCLK. "
"In Suspend Power Well.
O P3V3_AUX NA Muxed with SLP_S5#.
Defaults to SLP_S5#. "
"In Core Power Well.
I P1V1_SSB PU Unmuxed. Defaults to
GPO. "
"In Core Power Well.
I P1V1_SSB NA Unmuxed. Defaults to
GPO. "
V A
ENDOR LTERNATE
U
SED
FUNCTION
FUNCTION
) (D )
EFAULT
SUS_STAT_
GPO
N (GPO)
SUSCLK
GPO
(GPO)
SLPS5_N
GPO
(GPO)
GPIO64
GPO
(GPO)
GPIO65
GPO
(GPO)
1-71
N
STATE ET
NET
AFTER CONNECT
NAME
RESET TO
connect
to PCIE
SLOT5
and
FM_RISE SLOT6
high
R_ID3_R3 and pull
up 4.75k
to
P3V3_A
UX
CPLD
CLK_33K_
via a
SUSCLK_ N/A N/A
10ohm
PLD
resistor
connect
to BMC
FM_SLPS
and N/A
N/A
5_N
NCT301
2S
connect
to Slot2
FM_RISE and pull
high P3V3
R_ID0 up P3V3
via
1Kohm
connect
to Slot6
FM_RISE and pull
N/A P3V3
R_ID1 up P3V3
via
1Kohm
GPIO L
IST
Reserv
ed for
JTAG
for
CPLD
on-line
update
CLK to
PLD
S5
Sleep
Control
PCIE
slot6
riser
PCIE
slot6
riser