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Note: The lookup table is not cleared by reset. The lookup table must be initialized by the local processor
before the Upstream Memory 2 Address range is used.
Figure 9. Lookup Table Entry Format
31
4.3.5
Forwarding of 64
The 21555 considers the host and local memory space above the 4 GB boundary to be shared. This means that the
21555 uses a flat address map in this space. Dual-address cycle (DAC) transactions are used for addressing above
the 4 GB boundary. The 21555 can forward dual-address cycle transactions both upstream and downstream. The
Downstream Memory 3 BAR is used to designate the address range for downstream DACs. Inverse decoding is
used for upstream DACs.
The Downstream Memory 3 BAR may be configured to be a 64-bit BAR by preloading the Downstream Memory 3
Upper 32 Bits Setup register bit [31] to a one. The Downstream Memory 3 Setup register bits [2:1] should be set to
10b. This implies that the memory range can be located anywhere in 64-bit address space. When this 64-bit
addressing option is used, the maximum window size changes from 2 GB (in the 32-bit case) to 2
When the preloaded window size for a 64-bit BAR is 2 GB or less, the space requested may be mapped either in
32-bit address space or 64-bit address space. In the former case, the upper 32 bits of the base address is zero and
transactions are forwarded as described in the previous section using direct offset address translation. When the
upper 32-bit base address is non-zero, the memory range is located above the 4 GB boundary.
When the Downstream Memory 3 Range is mapped above the 4 GB boundary, primary bus transactions falling into
this address range are forwarded downstream with no address translation performed. Any 64-bit address
transactions on the secondary bus falling outside of the Downstream Memory 3 address range are forwarded
upstream, again with no address translation. This is similar to the forwarding mechanisms of a transparent PPB
(21154) and is illustrated in
Note: Since the use of BARs restricts the alignment of the address range to the window size, the
Downstream Memory 3 address range can never straddle the 4 GB boundary. The base address of
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Translated Base Address
Bit Address Memory Transactions
-
Figure
10.
18 17
Translated Base Address
or Reserved
Prefetchable
Address Decoding
8 7
4
3 2
1 0
Reserved
Reserved
Reserved
Valid
A7467-01
63
bytes.
41
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