Writing Vpd Information - Intel 21555 User Manual

VPD Support
15.2

Writing VPD Information

A write can occur only to the last 2 Kb (256 bytes) of VPD Space. Valid VPD byte addresses for write operations
are 17F:080h. To write VPD information from the serial ROM, the following steps must be taken:
1. The VPD data register is written with 4 bytes of data. Byte 0 contains the data to be written to the location
referenced by the VPD byte address. The value in bytes 3:1 of the VPD Data register is written to successive
byte locations in VPD space.
2. The VPD address and VPD Flag bits are written. This requires a write to bytes E7:E6h, where the low 9 bits
carry the VPD byte address and bit 15 is a 1, indicating a write operation. The 21555 adds the VPD base
address, 080h, to the VPD byte address to obtain the serial ROM address and perform a write of 4 bytes. The
VPD address has no alignment requirements; it can start on any byte boundary.
3. The VPD Flag bit is polled. When the 21555 returns a 0, the write is complete.
When a write is attempted to a location in the first 1Kb of serial ROM space (address bits 8:7 is 00b), the 21555
does not perform the write operation and clears the flag bit immediately. When the VPD byte address is one of the
last three byte locations in VPD space, the 21555 only completes those writes to the end of VPD space, that is, it
performs either a 3-, 2-, or 1-byte write.
The 21555 tracks whether the serial ROM is enabled for writes. If the serial ROM is write disabled when a VPD
write is attempted, the 21555 first automatically performs a write enable operation to the serial ROM. The 21555
does not automatically perform this operation for serial writes using the CSR mechanism.
The VPD Address and VPD Data registers should not be written while any other VPD, serial ROM, or parallel
ROM (PROM) operation is taking place, otherwise results are unpredictable.
120 21555 Non-Transparent PCI-to-PCI Bridge User Manual