Delayed Write Transactions - Intel 21555 User Manual

PCI Bus Transactions
5.3

Delayed Write Transactions

The 21555 uses delayed transactions when forwarding I/O writes from one PCI interface to the other. Delayed
transactions are also used for CSR or configuration register writes that cause the 21555 to initiate a transaction on
the opposite interface, such as:
•
CSR or configuration register write access that causes the 21555 to initiate a configuration write transaction.
•
CSR write access that causes the 21555 to initiate an I/O write transaction.
When an I/O write intended for the opposite PCI bus is first initiated, the 21555 returns a target retry. When the
delayed transaction queue is not full and if a transaction having the same address and bus command does not
already exist in the delayed transaction queue, the 21555 queues the transaction information:
•
Including address.
•
Bus command.
•
Write data.
•
Byte enables.
Note: The byte enables are not checked when the 21555 decides whether to queue a delayed write
transaction.
•
When the transaction queued is a result of an I/O Configuration Data register write, the 21555 queues the
appropriate data based on the type of access desired, the address and data contained in the corresponding
registers, and the byte enables used for the register access. This phase of the delayed transaction is called a
delayed write request (DWR).
•
The 21555 requests the target bus and initiates the delayed write transaction as soon as the 21555 ordering
rules allow. (See Section
write transaction. The 21555 completes the transaction on the target bus and adds the completion status to the
queue. Completion status contains the type of termination (TRDY#, target abort, master abort) and whether
PERR# assertion was detected. This phase of the delayed transaction is called the delayed write completion
(DWC).
When the 21555 receives 2
conditionally asserts SERR# on the initiator bus. See
retry counter disable bit in the Chip Control 0 Configuration register. When the transaction is discarded before
completion, the 21555 returns a target abort to the initiator.
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5.7). The 21555 always performs a single 32-bit data phase when initiating a delayed
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consecutive target retries from the target, it discards the delayed write request and
Chapter 12. This retry counter may be disabled by setting the
21555 Non-Transparent PCI-to-PCI Bridge User Manual