Table of Contents
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Contents
1
Preface ..........................................................................................................................................11
1.1
Cautions and Notes ............................................................................................................12
1.2
Data Units ...........................................................................................................................12
1.3
Numbering ..........................................................................................................................12
1.4
Signal Nomenclature ..........................................................................................................13
1.5
Register Abbreviations........................................................................................................14
2
Introduction....................................................................................................................................15
2.1
Comparing a 21555 to a Transparent PPB.........................................................................15
2.2
Architectural Overview........................................................................................................18
2.2.1
Data Buffers ...........................................................................................................18
2.2.2
Registers................................................................................................................18
2.2.3
Control Logic..........................................................................................................18
2.3
Special Applications............................................................................................................20
2.3.1
Primary Bus VGA Support .....................................................................................20
2.3.2
Secondary Bus VGA Support ................................................................................20
2.4
Programming Notes ............................................................................................................20
2.4.1
Addressing .............................................................................................................20
2.4.2
Transaction Forwarding .........................................................................................21
2.4.3
ROM Access ..........................................................................................................21
3
Signal Descriptions ........................................................................................................................23
3.1
Primary PCI Bus Interface Signals .....................................................................................24
3.2
Primary PCI Bus Interface 64-Bit Extension Signals ..........................................................26
3.3
Secondary PCI Bus Interface Signals.................................................................................28
3.4
Secondary PCI Bus Interface 64-Bit Extension Signals .....................................................30
3.5
Miscellaneous Signals ........................................................................................................31
4
Address Decoding .........................................................................................................................33
4.1
CSR Address Decoding ......................................................................................................34
4.2
Expansion ROM Address Mapping (Decoding) ..................................................................34
4.3
Memory 0 Transaction Address Decoding..........................................................................34
4.3.1
Using the BAR Setup Registers.............................................................................35
4.3.2
Direct Address Translation ....................................................................................36
4.3.3
Lookup Table Based Address Translation .............................................................37
4.3.4
Lookup Table Entry Format ...................................................................................40
4.3.5
Forwarding of 64-Bit Address Memory Transactions.............................................41
4.4
I/O Transaction Address Decoding.....................................................................................42
4.4.1
Indirect I/O Transaction Generation.......................................................................42
4.4.2
Subtractive Decoding of I/O Transactions .............................................................44
4.5
Configuration Accesses ......................................................................................................44
4.5.1
Type 0 Accesses to 21555 Configuration Space ...................................................44
4.5.2
Initiation of Configuration Transactions by 21555..................................................45
4.6
21555 Bar Summary ...........................................................................................................47
5
PCI Bus Transactions....................................................................................................................49
5.1
Transactions Overview .......................................................................................................49
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Contents
3
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