Control And Status Registers; Csr Address Map - Intel 21555 User Manual

List of Registers
Table 32. Configuration Space Address Register (Sheet 5 of 5)
Byte
Offset
(Hex)
EC
ED
EE
FF:F0
16.3

Control and Status Registers

The control and status registers are memory mapped in the Primary CSR and Memory 0 Base Address window and
the Secondary CSR Base Address window. These registers are I/O mapped in the Primary CSR I/O BAse Address
window and the Secondary CSR I/O Base Address window. Offsets are referenced from these base addresses.
Table 33 lists the CSR summary. 017:014
Table 33. CSR Address Map (Sheet 1 of 5)
Byte
Offset
(Hex)
003:000
007:004
00B:008
00F:00C
010
011
013:012
017:014
126
Register Name
CompactPCI Hot-Swap
Capability Identifier and Next
Pointer Register, page 189
Hot-Swap Cap ID
Hot-Swap Next Ptr
CompactPCI Hot-Swap Control
Register, page 189
Hot-Swap Control
Reserved
Register Name
Downstream and Upstream Configuration
Address Registers, page 141
Downstream Configuration Address
Downstream Configuration Data and
Upstream Configuration Data Registers,
page 142
Downstream Configuration Data
Downstream and Upstream Configuration
Address Registers, page 141
Upstream Configuration Address
Downstream Configuration Data and
Upstream Configuration Data Registers,
page 142
Upstream Configuration Data
Configuration Own Bits Register, page 142
Configuration Own Byte 0
Configuration Own Byte 1
Configuration CSR, page 143
Configuration CSR
Downstream I/O Address and Upstream I/O
Address Registers, page 144
Downstream I/O Address
Reset Value
Preload
(Hex)
06 —
00 —
00x1000b —
00000000 —
Reset Value
Indeterminate
Indeterminate
Indeterminate
Indeterminate
00
00
0000
Indeterminate
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Write Read
Access Access
Secondary N
N N
Y N
N Y
Write Access Read Access
Primary Y
Primary Primary
Secondary Y
Secondary Secondary
Primary Read-
N
0-to-set
Secondary
N
Read-0-to-set
Y Y
Primary Y