Init Registers; Power Management Ecp Id And Next Pointer Register - Intel 21555 User Manual

Table 117. Secondary SERR# Disable Register
Upstream Delayed
1 Read Transaction
Discarded
Upstream Delayed
2 Write Transaction
Discarded
Upstream Posted
3
Write Data Discarded
Target Abort during
4 Upstream Posted
Write
Master Abort during
5 Upstream Posted
Write
Upstream Posted
6
Write Parity Error
7 Reserved
16.13

Init Registers

This section describes the Power management, Reset, and Hot-swap registers. See
information.
Table 118. Power Management ECP ID and Next Pointer Register
• Primary byte offset: DD:DCh
• Secondary byte offset: DD:DCh
Bit Name
7:0 PM ECP ID
15:8 PM Next Ptr R
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Disables s_serr_l assertion when the 21555 discards an upstream
delayed read transaction request after receiving 2
R/W
from the primary bus target.
Reset value is 0
Disables s_serr_l assertion when the 21555 discards an upstream
delayed write transaction request after receiving 2
R/W
from the primary bus target.
Reset value is 0
Disables s_serr_l assertion when the 21555 discards an upstream
posted write transaction after receiving 2
R/W
primary bus target.
Reset value is 0
Disables s_serr_l assertion when the 21555 detects a target abort
on the primary interface in response to an upstream posted write.
R/W
Reset value is 0
Disables s_serr_l assertion when the 21555 detects a master abort
on the primary interface when initiating an upstream posted write.
R/W
Reset value is 0
Disables s_serr_l assertion when the 21555 detects p_perr_l
asserted during an upstream posted write.
R/W
Reset value is 0
R Reserved. Returns 0 when read.
R/W Description
Power Management Enhanced Capabilities Port ID. Read only as 01h to identify
R
these ECP registers as Power Management registers.
Pointer to next ECP registers. Reads as E4 to indicate the first register of the
next set of ECP registers, which support Vital Product Data, and resides at offset
E4h.
List of Registers
24
target retries
24
target retries
24
target retries from the
Chapter 2 for theory of operation
185