Intel 21555 User Manual page 83

Table 21. PROM Interface Signals (Sheet 2 of 2)
Signal
Name
pr_ale_l
pr_clk
pr_cs_l/
pr_rdy
pr_rd_l
pr_wr_l
sr_cs
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Type Description
PROM address latch enable/chip select decoder enable. The signal pr_ale_l is used
to enable the PROM address latches. The 21555 asserts pr_ale_l low when it drives
the first eight bits of the 24-bit address on pr_ad[7:0], and keeps it asserted until the
O last eight bits of the address are driven. The address is shifted through three octal
D-registers while pr_ale_l is low. When in multiple device mode, pr_ale_l is also
used for a chip select enable. When pr_ale_l is high, the upper latched address lines
are decoded with external circuitry to assert device chip enables.
PROM address latch clock output. The signal pr_clk is used to clock the three
O address registers needed to demultiplex the address. Signal pr_clk is divided by two
when 33 MHz or pr_clk is divided by four when 66 MHz.
PROM chip select or device ready. For a single device attachment, pr_cs_l is used
for the PROM chip select. The 21555 asserts pr_cs_l low after the address is shifted
out and demultiplexer through the three external octal registers. The 21555 deasserts
pr_cs_l according to the access time specified in the
O/I
Register" on page 178. When in multiple device mode, pr_cs_l is reconfigured as a
device ready (pr_rdy) input. When pr_cs_l is driven low while the read or write strobe
is asserted, the assertion time of the read or write strobe is extended by the amount
of time the device ready signal is held low.
PROM read strobe. This signal controls the output enable signal of the PROM. The
21555 asserts pr_rd_l to enable the ROM to drive read data on pr_ad[7:0]. The
O
21555 samples this read data on the deasserting (rising) edge of pr_rd_l. The timing
of pr_rd_l with respect to the chip select is dictated by the read strobe mask.
PROM write strobe. This signal controls the write enable signal of the PROM. The
21555 asserts pr_wr_l when it drives write data to the ROM on pr_ad[7:0]. Write
O
data is held stable until the deasserting (rising) edge of pr_wr_l. The timing of
pr_wr_l with respect to the chip select is dictated by the write strobe mask.
Serial ROM chip select. The 21555 drives this signal high to enable the serial ROM
O for a read or write. The serial ROM operation uses pins pr_ad[2:0] for data in, data
out, and clock.
Parallel ROM Interface
Table 112, "ROM Control
83