Primary Clear Irq And Secondary Clear Irq Registers; Primary Set Irq And Secondary Set Irq Registers - Intel 21555 User Manual

Table 102. Primary Clear IRQ and Secondary Clear IRQ Registers
These registers affect primary and secondary interrupts in the same way and are described together.
Byte Offset:
Bit Name
15:0 CLR_IRQ
Table 103. Primary Set IRQ and Secondary Set IRQ Registers
These registers affect primary and secondary interrupts in the same way and are described together.
Offsets
Byte
Bit Name
15:0 SET_IRQ
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Primary Clear IRQ
099:098h
R/W Description
This register controls the state of the Primary or Secondary Interrupt
Request bits.
• When 0, Does not cause the corresponding primary or secondary
interrupt signal to be asserted.
• When 1, the primary or secondary interrupt signal is asserted when
R/W1TC the corresponding IRQ Mask bit is zero.
Writing a 1 to a bit in this register clears the corresponding interrupt
request bit to 0. Writing a 0 to any bit in this register has no effect.
Reading this register returns the current status of the interrupt
request bits.
• Reset value is 0
Primary Set IRQ
09D:09Ch
R/W Description
This register controls the state of the Primary or Secondary Interrupt
Request bits.
• When 0, Does not cause the corresponding primary or secondary
interrupt signal to be asserted.
• When 1, the primary or secondary interrupt signal is asserted if the
R/W1TS corresponding IRQ Mask bit is zero.
Writing a 1 to a bit in this register sets the corresponding interrupt
request bit to 1. Writing a 0 to any bit in this register has no effect.
Reading this register returns the current status of the interrupt
request bits.
• Reset value is 0
List of Registers
Secondary Clear IRQ
09B:09Ah
Secondary Set IRQ
09F:09Eh
173