Subsystem Vendor Id Register; Subsystem Id Register; Enhanced Capabilities Pointer Register; Primary And Secondary Interrupt Line Registers - Intel 21555 User Manual

List of Registers
Table 69. Subsystem Vendor ID Register
• Primary byte offset: 2D:2Ch and 6D:6Ch
• Secondary byte offset: 6D:6Ch and 2D:2Ch
Bit Name
Subsystem
15:0
Vendor ID
Table 70. Subsystem ID Register
• Primary byte offset: 2F:2Eh and 6F:6Eh
• Secondary byte offset: 6F:6Eh and 2F:2Eh
Bit Name
Subsystem
15:0
ID
Table 71. Enhanced Capabilities Pointer Register
Offsets
Primary byte
Secondary byte
Bit Name
7:0 ECP
Pr
Table 72. Primary and Secondary Interrupt Line Registers
Offsets
Primary byte
Secondary byte
Bit Name
7:0 Interrupt Line
154
R/W Description
Identifies the vendor of the add
R/(WS)
initialized by either the local processor or by serial ROM preload.
R/W Description
Identifies the vendor
R/(WS)
initialized by either the local processor or by serial ROM preload.
ECP
34h and 74h
34h and 74h
R/W Description
Pointer to the first set of ECP registers. Returns DCh to indicate that the first
set of ECP registers begins at configuration offset DCh. For the 21555, this
R
points to the Power Management registers.
Reset value is DCh
Primary Interrupt Line
3Ch
7Ch
R/W Description
This register is used to communicate interrupt line routing information for
the corresponding interface. This register must be initialized by
initialization code so a default state after reset assertion is not specified.
R/W
Initialization code writes this register with a value indicating to which input
of the system interrupt controller the 21555 bus interrupt signal pin INTA#
is connected.
21555 Non-Transparent PCI-to-PCI Bridge User Manual
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in card or subsystem. This register is
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specific device ID for subsystem. This register is
Secondary Interrupt Line
7Ch
3Ch