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PCI Bus Transactions
5.2
Posted Write Transactions
This section discusses the following Posted Write Transactions:
•
Section 5.2.1, "Memory Write Transactions" on page
•
Section 5.2.2, "Memory Write and Invalidate Transactions" on page
•
Section 5.2.3, "64-bit Extension Posted Write Transaction" on page
•
Section 5.2.4, "Write Performance Tuning Options" on page
The 21555 posts all memory write and Memory Write and Invalidate (MWI) transactions that are to be forwarded
from one interface to the other. The 21555 accepts write data into its buffers without wait states until one of the
following conditions occur:
•
The initiator ends the transaction.
•
An aligned address boundary is reached.
•
The posted write queue fills.
Aligned address disconnect boundaries for memory write and MWI transactions are listed in
Section
5.2.2.
The 21555 does not initiate a memory write transaction on the target bus until at least a cache line amount of data is
posted. When the transaction consists of less than a cache line, the 21555 waits until the entire burst is posted. For
all posted write behavior dependent on the cache line size (CLS), the 21555 uses the cache line value corresponding
to the target interface. For downstream transactions the secondary bus cache line size is used, and for upstream
transactions the primary cache line size is used. When the cache line size corresponding to the target bus is not set
to a valid value, the 21555 uses a value of 8 Dwords for this purpose. Possible valid values are 8, 16 and 32
Dwords.
Note: A cache line amount of data refers to the number of Dwords only, no address alignment is inferred.
The 21555 continues the transaction to the target as long as write data is available or the transaction has terminated
on the initiator bus. Otherwise, the 21555 ends the transaction when a queue-empty condition is detected or when
all write data has been delivered for this transaction. The 21555 does not insert master wait states when initiating
posted writes.
Note: A queue empty condition occurs when less than a cache line amount of data exists in the posted
write buffers. This does not imply any address alignment; in this context cache line refers only to
the number of Dwords, and the transaction is not necessarily ended on a cache line boundary.
When the 21555 receives 2
the 21555 discards the posted write transaction and conditionally asserts SERR# on the initiator bus (see
Chapter
12). This retry counter can be disabled by setting the retry counter disable bit in the Chip Control 0
configuration register. The 21555 also conditionally asserts SERR# on the initiator bus when a target abort or
master abort is detected on the target bus in response to the posted write.
50
24
consecutive target retries from the target when attempting to deliver posted write data,
51.
51.
52.
52.
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Section 5.2.1
and
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