Prom Write By Csr Access - Intel 21555 User Manual

Parallel ROM Interface
8.4

PROM Write by CSR Access

Byte writes of the PROM can be performed by CSR access of the
Table 111, "ROM Address Register" on page
is performed as follows:
1. The initiator writes the byte address offset to the ROM Address register.
2. The initiator writes one byte of write data into the ROM Data register.
3. The initiator writes the PROM Start bit to a 1, Serial ROM Start bit to a 0, and the ROM Read/Write Control bit
to a 1 in the
Table 112, "ROM Control Register" on page 178
4. When the initiator reads the PROM Start bit in the
is complete.
When a byte write to the PROM is performed, the 21555 follows this sequence on the ROM interface, also shown
in Figure 16:
1. The 21555 drives address bits [23:16] on the pr_ad[7:0] pins and asserts the address register enable, pr_ale_l.
2. The 21555 drives pr_clk high, latching address bits [23:16] into the first external register.
3. The 21555 drives pr_clk low.
4. The 21555 drives address bits [15:8] on the pr_ad[7:0] pins.
5. The 21555 drives pr_clk low, latching address bits [15:8] into the first external register, and address bits
[23:16] into the second external register.
6. The 21555 drives pr_clk low.
7. The 21555 drives address bits [7:0] on the pr_ad[7:0] pins.
8. The 21555 drives pr_clk high, latching address bits [7:0] into the first external register, address bits [15:8] into
the second external register, and address bits [23:16] into the third external register. All the ROM address and
control bits are now driven to the appropriate ROM pins.
9. The 21555 deasserts the address register enable, pr_ale_l.
10. The 21555 drives the write data on pr_ad[7:0].
11. The 21555 asserts the pr_cs_l and pr_wr_l pins according to the strobe setup timing specified by the Strobe
Mask in the ROM Setup register.
12. The 21555 deasserts pr_wr_l according to the strobe timing in the ROM Setup register, and deasserts the
pr_cs_l according to the access time in the ROM Setup register.
13. The 21555 clears the PROM Start bit in the
86
Table 112, "ROM Control Register" on page 178
178, and Table 110, "ROM Data Register" on page
This can be done with the same CSR access.
Table 112, "ROM Control Register" on page 178
Table 112, "ROM Control Register" on page 178
21555 Non-Transparent PCI-to-PCI Bridge User Manual
,
177. A byte write
as a 0, the access
.