Intel 21555 User Manual page 181

Table 114. Serial Preload Sequence (Sheet 2 of 3)
Not all of the bits in the sequence are used. Bits that are not used must be 0 (zero)
Byte
offset
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Description
Subsystem ID [7:0]
Subsystem ID [15:8]
Primary Minimum Grant
Primary Maximum Latency
Secondary Programming Interface
-
Secondary Sub Class Code
Secondary Base Class Code
Secondary Minimum Grant
Secondary Maximum Latency
Downstream Memory 0 Setup [7:0]. Bits [0, 7:4] are not loaded and should be 0.
Downstream Memory 0 Setup [15:8]. Bits [11:8] are not loaded and should be 0.
Downstream Memory 0 Setup [23:16]
Downstream Memory 0 Setup [31:24]
Downstream I/O or Memory 1 Setup [7:0]. Bits [5:4] are not loaded and should be 0.
Downstream I/O or Memory 1 Setup [15:8]
Downstream I/O or Memory 1 Setup [23:16]
Downstream I/O or Memory 1 Setup [31:24]
Downstream Memory 2 Setup [7:0]. Bits [0, 7:4] are not loaded and should be 0.
Downstream Memory 2 Setup [15:8]. Bits [11:8] are not loaded and should be 0.
Downstream Memory 2 Setup [23:16]
Downstream Memory 2 Setup [31:24]
Downstream Memory 3 Setup [7:0]. Bits [0, 7:4] are not loaded and should be 0.
Downstream Memory 3 Setup [15:8]. Bits [11:8] are not loaded and should be 0.
Downstream Memory 3 Setup [23:16]
Downstream Memory 3 Setup [31:24]
Downstream Memory 3 Setup Upper 32 Bits [7:0]
Downstream Memory 3 Setup Upper 32 Bits [15:8]
Downstream Memory 3 Setup Upper 32 Bits [23:16]
Downstream Memory 3 Setup Upper 32 Bits [31:24]
• Bit [0]: Primary Expansion ROM Setup [24] (enable)
• Bits [3:1]: Not loaded. Should be 0.
• Bits [7:4]: Primary Expansion ROM Setup [15:11]
Primary Expansion ROM Setup [23:16]
Upstream I/O or Memory 0 Setup [7:0]. Bits [5:4] are not loaded and should be 0.
Upstream I/O or Memory 0 Setup [15:8]
Upstream I/O or Memory 0 Setup [23:16]
List of Registers
181