Csr Address Decoding; Expansion Rom Address Mapping (Decoding); Memory 0 Transaction Address Decoding - Intel 21555 User Manual

Address Decoding
4.1

CSR Address Decoding

The 21555 implements a set of CSRs that are mapped in memory or in I/O space. The registers are mapped
independently on the primary and secondary interfaces. The following BARs are used for CSR mapping:
•
The primary CSR and:
— Downstream Memory 0 BAR is for mapping in primary bus memory address space. The Lower 4KB of
this range used to map the 21555 CSRs.
— I/O BAR is for mapping in primary bus I/O space.
•
The secondary CSR:
— Memory BAR is for mapping in secondary bus memory address space.
— I/O BAR is for mapping in secondary bus I/O space.
The primary BARs are located in the 21555 primary bus configuration space, and the secondary BARs are located
in the 21555 secondary bus configuration space. The memory BARs request 4 KB each (minimum size for Primary
CSR and Downstream Memory 0 BAR), and the I/O BARs request 256 bytes each.
4.2

Expansion ROM Address Mapping (Decoding)

The 21555 implements one BAR, the Primary Expansion Read Only Memory (ROM) BAR, to map the expansion
ROM that can be attached to the 21555. The Expansion ROM can be mapped into primary bus address space only,
and is not accessible through a BAR from the secondary bus. The size of the Primary Expansion ROM BAR is
programmable through the Primary Expansion ROM Setup register in device-specific configuration space. The size
may vary from 4 KB to 16 MB by powers of 2. The Primary Expansion ROM BAR can also be disabled through
theSetup register so that it does not request space when the expansion ROM is not implemented.
4.3

Memory 0 Transaction Address Decoding

The BARs can be enabled to decode and forward memory transactions to the opposite interface. The 21555
implements primary interface and secondary interface BARs:
•
The downstream BARs are in primary configuration space. The BARs decode transactions on the primary bus
to be forwarded to the secondary bus.
— Primary CSR and Downstream Memory 0.
— For addresses above the low 4 KB in this address range.
— Upstream I/O or Memory 0.
— Upstream Memory 1.
— Upstream Memory 2.
•
The upstream BARs are in secondary configuration space. The BARs decode transactions on the secondary
bus to be forwarded to the primary bus.
— Downstream I/O or Memory 1.
— Downstream Memory 2.
— Downstream Memory 3.
34 21555 Non-Transparent PCI-to-PCI Bridge User Manual