Intel 21555 User Manual page 182

List of Registers
Table 114. Serial Preload Sequence (Sheet 3 of 3)
Not all of the bits in the sequence are used. Bits that are not used must be 0 (zero)
Byte
offset
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
182
Description
Upstream I/O or Memory 0 Setup [31:24]
Upstream Memory 1 Setup [7:0]. Bits [0, 7:4] are not loaded and should be 0.
Upstream Memory 1 Setup [15:8]. Bits [11:8] are not loaded and should be 0.
Upstream Memory 1 Setup [23:16]
Upstream Memory 1 Setup [31:24]
Chip Control 0 [7:0]
Chip Control 0 [15:8]. Bits [13:12] are not loaded and should be 0.
Chip Control 1 [7:0]
Chip Control 1 [15:8]
Arbiter Control [7:0]
Arbiter Control [15:7]. Bits [15:10] are not loaded and should be 0.
Primary SERR# Disable. Bit [7] is not loaded and should be 0.
Secondary SERR# Disable. it [7] is not loaded and should be 0.
Power Management Data 0
Power Management Data 1
Power Management Data 2
Power Management Data 3
Power Management Data 4
Power Management Data 5
Power Management Data 6
Power Management Data 7
Reserved
• [1:0] 00b (Reserved)
• [2] BiST Supported
• [3] Power Management Data Register Enable
• [5:4] Power Management Control and Status [14:13]
• [7:6] Power Management Capabilities Register [1:0]
• [0] Power Management Capabilities Register [2]
• [1] Power Management Capabilities Register [5]
• [7:2] Power Management Capabilities Register [14:9]
21555 Non-Transparent PCI-to-PCI Bridge User Manual