Intel 21555 User Manual page 128

List of Registers
Table 33. CSR Address Map (Sheet 3 of 5)
Byte
Offset
(Hex)
057:054
05B:058
05F:05C
063:060
067:064
06B:068
06F:06C
073:070
077:074
07B:078
07F:07C
083:082
085:084
087:086
08B:088
08F:08C
128
Register Name
I2O Outbound Post_List Head Pointer,
page 167
I20 Outbound Post Head Pointer
I2O Inbound Post_List Counter, page 168
I20 Inbound Post Counter
I2O Inbound Free_List Counter, page 168
I20 Inbound Free Counter
I2O Outbound Post_List Counter, page 169
I20 Outbound Post Counter
I2O Outbound Post_List Counter, page 169
I20 Outbound Free Counter
Downstream Memory 0, 2, 3, and Upstream
Memory 1 Translated Base Register, page
137
Downstream Memory 0 Translated Base
Downstream I/O or Memory 1 and
Upstream I/O or Memory 0 Translated Base
Register, page 136
Downstream I/O or Memory 1 Translated
Base
Downstream Memory 0, 2, 3, and Upstream
Memory 1 Translated Base Register, page
137
Downstream Memory 2 Translated Base
Downstream Memory 3 Translated Base
Downstream I/O or Memory 1 and
Upstream I/O or Memory 0 Translated Base
Register, page 136
Upstream I/O or Memory 0 Translated Base
Downstream Memory 0, 2, 3, and Upstream
Memory 1 Translated Base Register, page
137
Upstream Memory 1 Translated Base
Chip Status CSR, page 170
Chip Status CSR
Chip Set IRQ Mask Register, page 170
Chip Set IRQ Mask
Chip Clear IRQ Mask Register, page 171
Chip Clear IRQ Mask
Upstream Page Boundary IRQ 0 Register,
page 171
Upstream Page Boundary IRQ 0
Upstream Page Boundary IRQ 1 Register,
page 172
Upstream Page Boundary IRQ 1
Reset Value
Indeterminate
00000000
00000000
00000000
00000000
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
0000
FFFF
FFFF
00000000
00000000
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Write Access Read Access
Y Y
Secondary Y
Secondary Y
Secondary Y
Secondary Y
Y Y
Y Y
Y Y
Y Y
Y Y
Y Y
W1TC Y
W1TS Y
W1TC Y
W1TC Y
W1TC Y