Interrupt And Scratchpad Registers; Primary And Secondary Pci Bus Interrupt Signals; Interrupt Support - Intel 21555 User Manual

Interrupt and Scratchpad Registers

This chapter presents the theory of operation information about the 21555 interrupt handling and about the 32-bit
scratchpad registers. See Chapter 16
11.1

Primary and Secondary PCI Bus Interrupt Signals

describes the primary and secondary PCI bus interrupt signals.
Table 26
Table 26. Primary and Secondary PCI Bus Interrupt Signals
Signal Name Type
p_inta_l
s_inta_l
11.2

Interrupt Support

The 21555 supports hardware to facilitate software-generated interrupts, as well as interrupts initiated by the 21555
activity. The 21555 has interrupt request status and interrupt mask bits for the following conditions:
•
I20 Inbound Post_List FIFO not empty.
— Cleared automatically when FIFO is empty.
— Asserts s_inta_l when the corresponding mask bit is zero.
•
I20 Outbound Post_List FIFO not empty.
— Cleared automatically when FIFO is empty.
— Asserts p_inta_l when the corresponding mask bit is zero.
•
Upstream memory read or write Dword transfer in Upstream Memory Range 2 addresses the last Dword in a
page.
— One event and enable bit for each of the 64 pages in Upstream Memory Range 2.
21555 Non-Transparent PCI-to-PCI Bridge User Manual
for specific information about these registers.
Description
Primary PCI bus interrupt. Signal p_inta_l is asserted by the 21555 when:
A primary doorbell register bit is set.
The I20 outbound queue is not empty.
OD
The subsystem event bit is set.
All of these conditions are individually maskable. When the corresponding event bit is
cleared or the I20 outbound queue is emptied, p_inta_l is deasserted. Signal p_inta_l
is pulled up through an external resistor.
Secondary PCI bus interrupt. Signal s_inta_l is asserted by the 21555 when:
A secondary doorbell register bit is set.
The I20 inbound queue is not empty.
A page boundary is reached when performing lookup table address translation.
OD
The 21555 transitions from a D1 or D2 power state to a D0 power state.
All of these conditions are individually maskable. Signal s_inta_l is deasserted when
the corresponding event bit is cleared, or when the I20 inbound queue is empty.
Signal s_inta_l is pulled up through an external resistor.
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