Downstream Memory 0, 2, 3, And Upstream Memory 1 Setup Registers - Intel 21555 User Manual

Non-transparent pci-to-pci bridge
Table of Contents

Advertisement

Table 44. Downstream Memory 0, 2, 3, and Upstream Memory 1 Setup Registers
These registers are used to program the type and size of their respective upstream and
downstream BARs.
Offsets
Primary byte
Secondary byte
Bit
Name
Type
0
Selector
2:1
Type
3
Prefetchable
11:4
Reserved
30:12
Size
31
BAR_Enable
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Downstream
Downstream
Memory 0 Setup
Memory 2 Setup
AF:ACh
B7:B4h
AF:ACh
B7:B4h
R/W
Description
Read only as 0 to indicate memory space is requested by the
R
corresponding memory BAR.
Type of space requested. Allowable values are:
• 00b to indicate that the space requested by the BAR may be located
anywhere in memory space
• 01b to indicate that it must be mapped below a 1MB boundary
R/(WS)
• 10b for Downstream Memory 3 Setup register to request a 64
Other values may yield unpredictable results.
Reset value is 00b.
Indicates whether the space requested by the BAR is prefetchable.
• When 0, not prefetchable.
R/(WS)
• When 1, prefetchable.
• Reset value is 0
R
Read only as 0.
These bits specify the size of the address range requested by the BAR.
• When a bit is 1, the corresponding bit in the BAR functions as a
readable and writable bit.
R/(WS)
• When a bit is 0, the corresponding bit in the BAR functions as a
-
read
only bit that always returns zero when read.
• Reset value is 0 (disabled), except for Downstream Memory 0 Setup
register, whose reset value is 7FFFFh (request 4 KB).
BAR enable.
Bit [31] of the Downstream Memory 0 Setup register always reads as 1,
indicating that the BAR cannot be disabled. When a bus master attempts to
write this bit with a 0, the 21555 returns all bits {31:12] of the setup register
as 1s (request 4KB).
• When the Upper 32 Bits Downstream Memory 3 Setup register bit [31]
is a 1, the corresponding BAR is enabled as a 64
R/(WS)
bit is part of the size field for the 64
• When 0, the corresponding BAR is disabled and reads as 0, with the
exception noted above.
• When 1, the corresponding BAR is enabled, with size and type
specified by this setup register.
• Reset value is 0, except for Downstream Memory 0 Setup register that
has a reset value of 1.
List of Registers
Downstream
Upstream
Memory 3 Setup
Memory 1 Setup
BB:B8h
CB:C8h
BB:B8h
CB:C8h
-
bit register, and this
-
bit BAR.
-
bit BAR
139

Advertisement

Table of Contents
loading

Table of Contents