Primary Serr# Disable Register; Secondary Serr# Disable Register - Intel 21555 User Manual

List of Registers
Table 116. Primary SERR# Disable Register
This register may be preloaded by serial ROM or programmed by the local processor before host
configuration. This register controls the ability of the 21555 to assert p_serr_l for a particular condition. When
the bit is a 0, the assertion of p_serr_l is not masked for this event.
When the bit is a 1, the assertion of p_serr_l is masked for this event.
• Primary byte offset: D4h
• Secondary byte offset: D4h
Bit Name
Downstream
Delayed
0 Transaction
Master
Time
Downstream
Delayed Read
1
Transaction
Discarded
Downstream
Delayed Write
2
Transaction
Discarded
Downstream
3 Posted Write
Data Discarded
Target Abort
during
4
Downstream
Posted Write
Master Abort
during
5
Downstream
Posted Write
Downstream
6 Posted Write
Parity Error
7 Reserved
Table 117. Secondary SERR# Disable Register
This register may be preloaded by serial ROM or programmed by the local processor before host
configuration. This register controls the ability of the 21555 to assert s_serr_l for a particular condition. When
the bit is a 0, the assertion of s_serr_l is not masked for this event.
When the bit is a 1, the assertion of s_serr_l is masked for this event.
• Primary byte offset: D5h
• Secondary byte offset: D5h
Bit Name
Upstream Delayed
0 Transaction Master
Timeout
184
R/W Description
Disables p_serr_l assertion when a downstream master time
is detected and the downstream transaction is discarded.
R/W
Reset value is 0
-
out
Disables p_serr_l assertion when 21555 discards a downstream delayed
read transaction request after receiving 2
R/W
target.
Reset value is 0
Disables p_serr_l assertion when 21555 discards a downstream delayed
write transaction request after receiving 2
R/W
bus target.
Reset value is 0
Disables p_serr_l assertion when 21555 discards a downstream posted
write transaction after receiving 2
R/W
Reset value is 0
Disables p_serr_l assertion when 21555 detects a target abort on the
secondary interface in response to a downstream posted write.
R/W
Reset value is 0
Disables p_serr_l assertion when the 21555 detects a master abort on the
secondary interface when initiating a downstream posted write.
R/W
Reset value is 0
Disables p_serr_l assertion when the 21555 detects s_perr_l asserted
during a downstream posted write.
R/W
Reset value is 0
R Reserved. Returns 0 when read.
R/W
R/W
24
target retries from secondary bus target.
Description
Disables s_serr_l assertion when an upstream master timeout
condition is detected and the upstream transaction is discarded.
Reset value is 0
21555 Non-Transparent PCI-to-PCI Bridge User Manual
-
out condition
24
target retries from secondary bus
24
target retries from secondary