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5.6.2
Transaction Termination Errors on the Target Bus
When the 21555 detects a target abort on the target bus, the 21555 sets the Received Target Abort in the Primary
and Secondary Status register. See
the 21555:
•
For delayed transactions, returns a target abort to the initiator and sets the Signaled Target Abort bit in the
Primary and Secondary Status register.
•
For posted write transactions, asserts SERR# on the initiator bus if the SERR# Enable for that interface is set,
and sets the Signaled System Error bit in the Primary and Secondary Status register.
When the 21555 detects a master abort on the target bus, the 21555 always sets Received Master Abort bit in
Primary and Secondary Status register. In addition, the 21555:
•
For delayed transactions when the Master Abort Mode bit is 0, returns TRDY# and, for reads, FFFFFFFFh to
the initiator. See
Table 77, "Chip Control 0 Register" on page
•
For delayed transactions when the Master Abort Mode bit is 1, returns a target abort and sets the Signaled
Target Abort bit in the Primary and Secondary Status register.
•
For posted write transactions, assert SERR# and set the Signaled System Error bit on the initiator bus if the
SERR# Enable for that interface is set and the SERR# Disable for Master Abort during Posted Write is clear.
5.7
Ordering Rules
The 21555 can queue and forward multiple transactions at once. Therefore, at any one time the 21555 has multiple
posted write and multiple delayed transaction requests and completions queued and traveling in the same and
opposite directions. The 21555 uses a set of ordering rules to dictate the order in which it initiates posted writes,
initiates delayed transaction requests, and returns delayed transaction completion status. These rules reflect both the
ordering constraints outlined in the PCI Local Bus Specification, Revision 2.2 as well as implementation choices
specific to the 21555.
Independent transactions on the primary and secondary buses only have a relationship when those transactions
cross the 21555. General ordering guidelines for transactions crossing the 21555 are:
•
The ordering relationship of a transaction with respect to other transactions is determined when the transaction
completes; that is, when a transaction ends with a termination other than target retry.
•
Requests terminated with target retry may be accepted and completed in any order with respect to other
transactions that have been terminated with target retry. When the order of completion of delayed requests is
important, the initiator should not start a second delayed transaction until the first one has been completed.
When more than one delayed transaction is initiated, the initiator should repeat all the delayed transaction
requests using some fairness algorithm; that is, reattempting a delayed transaction cannot be contingent on
completion of another delayed transaction, otherwise a deadlock can occur. This deadlock is avoided with an
out-of-order delivery and completion.
•
Write transactions flowing in one direction have no ordering requirements with respect to write transactions
flowing in the other direction. The 21555 can accept posted writes on both interfaces at the same time, as well
as initiate posted writes on both interfaces at the same time.
•
The acceptance of a posted memory write as a target can never be contingent on the completion of a
non-posted transaction as a master. This is true of the 21555 and must also be true of other bus agents;
otherwise, a deadlock can occur.
•
The 21555 accepts posted writes regardless of the state of completion of any delayed transactions being
forwarded across the bridge.
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Table 62, "Primary and Secondary Status Registers" on page
PCI Bus Transactions
156.
150. In addition,
61
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