I2O Registers; I2O Outbound Post_List Status; I2O Outbound Post_List Interrupt Mask; I2O Inbound Post_List Status - Intel 21555 User Manual

16.6

I2O Registers

This section contains a description of the I2O registers. See
Table 81. I2O Outbound Post_List Status
Byte Offset: 33:30h
Bit Name
2:0 Reserved
Outbound
3
Post Status
31:4 Reserved
Table 82. I2O Outbound Post_List Interrupt Mask
Byte Offset: 37:34h
Bit Name
2:0 Reserved
Outbound Post
3
Mask
31:4 Reserved
Table 83. I2O Inbound Post_List Status
Byte Offset: 3B:38h
Bit Name
2:0 Reserved
Inbound Post
3
Status
31:4 Reserved
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Chapter 14
R/W Description
R Reserved. Read only as 0.
Reflects the status of the Outbound Post_List.
• When 0, the Outbound Post_List is empty. The 21555 deasserts
p_inta_l (unless it is asserted for other reasons).
R
• When 1, the Outbound Post_List is not empty. When the Outbound
Post_List Interrupt Mask bit is zero, the 21555 asserts p_inta_l as long
as this status bit is set.
• Reset value is 0
R Reserved. Read only as 0.
R/W Description
R Reserved. Read only as 0.
Interrupt mask for Outbound Post_List Status.
• When 0, the 21555 asserts p_inta_l when the Outbound
Post_List Status bit is a 1.
R/W
• When 1, the 21555 does not assert p_inta_l when the
Outbound Post_List Status bit is a 1.
• Reset value is 1
R Reserved. Read only as 0.
R/W Description
R Reserved. Read only as 0.
Reflects the status of the Inbound Post_List.
• When 0, the Inbound Post_List is empty. The 21555 deasserts
s_inta_l (unless it is asserted for other reasons).
R
• When 1, the Inbound Post_ List is not empty. When the
Inbound Post_List Interrupt Mask bit is zero, the 21555 asserts
s_inta_l as long as this status bit is set.
• Reset value is 0
R Reserved. Read only as 0.
List of Registers
for theory of operation information.
165