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List of Registers
Table 104. Primary Clear IRQ Mask and Secondary Clear IRQ Mask Registers
These registers affect primary and secondary interrupts in the same way and are described
Byte Offset:
Bit
Name
15:0
CLR_IRQM
Table 105. Primary Set IRQ Mask and Secondary Set IRQ Mask Registers
These registers affect primary and secondary interrupts in the same way and are described together.
Offsets
Byte
Bit
Name
15:0
SET_IRQM
16.8
Scratchpad Registers
See
Chapter 11
for theory of operation information.
Table 106. Scratchpad 0 Through Scratchpad 7 Registers (Sheet 1 of 2)
Bit
Name
31:0
SCRATCH0
31:0
SCRATCH1
31:0
SCRATCH2
174
Primary Clear IRQ Mask
0A1:0A0h
R/W
Description
• When 0, an interrupt is generated on the 21555's primary or
secondary interface when the corresponding Primary or
Secondary Interrupt Request bit is a 1.
• When 1, the corresponding interrupt request bit cannot generate
an interrupt.
R/W1TC
Writing a 1 to a bit in this register clears the IRQ Mask bit to 0.
Writing a 0 to any bit in this register has no effect. Reading this
register returns the current status of the IRQ Mask bits.
• Reset value is FFFFFFFFh
Primary Set IRQ Mask
0A5:0A4h
R/W
Description
• When 0, an interrupt is generated on the 21555's primary or
secondary interface when the corresponding Primary or
Secondary Interrupt Request bit is a 1.
• When 1, the corresponding interrupt request bit cannot
generate an interrupt.
R/W1TS
Writing a 1 to a bit in this register sets the IRQ Mask bit to 1.
Writing a 0 to any bit in this register has no effect. Reading this
register returns the current status of the IRQ Mask bits.
• Reset value is FFFFFFFFh
R/W
Byte Offset:
R/W
0AB:0A8h
R/W
0AF:0ACh
R/W
0B3:0B0h
21555 Non-Transparent PCI-to-PCI Bridge User Manual
Secondary Clear IRQ Mask
0A3:0A2h
Secondary Set IRQ Mask
0A7:0A6h
Description
32-bit scratchpad register 0.
32-bit scratchpad register 1.
32-bit scratchpad register 2.
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