Prom Dword Read; Prom Write Timing - Intel 21555 User Manual

.
Figure 16. PROM Write Timing
p_clk
pr_clk
pr_ad[7:0]
d[7:0]
pr_cs_l
pr_wr_l
pr_ale_l
a[7:0]
a[15:8]
a[23:16]
8.5

PROM Dword Read

A Dword read is performed on the PROM interface when a read is initiated on the primary bus whose address falls
into the address range defined by the
memory read through the
target retry to the initiator. The 21555 performs four consecutive byte reads of the ROM. When the four byte reads
are complete, the 21555 returns the read data to the initiator on the next read attempt to that address to complete the
delayed transaction. The 21555 automatically sets the PROM Start/Busy bit upon initiation of the read and clears
the bit when the ROM read is complete.
Note: The 21555 uses the ROM Address CSR to hold for comparison the address decoded in the Primary
Expansion ROM address space. The CSR access method should not be used for the PROM when
reads to the PROM through the
taking place, because the address for the CSR access can become corrupted by a Expansion ROM
BAR read.
The delayed transaction mechanism for the expansion ROM BAR does not support multiple masters. Assume the
21555 completes a ROM Dword read on the ROM interface, but before the data is returned to the master a
transaction using a different offset in the expansion ROM BAR range is initiated. The 21555 discards the current
completed transaction and queues the second transaction. When the first transaction had not been completed on the
ROM interface, a target retry would have been returned.
21555 Non-Transparent PCI-to-PCI Bridge User Manual
A3 A2
A3
Table 107, "Primary Expansion ROM BAR" on page
Table 107, "Primary Expansion ROM BAR" on page 175
Table 107, "Primary Expansion ROM BAR" on page 175
A1 Write Data [7:0]
A2 A1 = Address[7:00]
A3 A2 = Address[15:8]
A3 = Address[23:16]
Parallel ROM Interface
A7471-01
175. The 21555 treats a
as a delayed read and returns a
are
87