System Clock Control Register (Sycc) - Fujitsu 8FX Hardware Manual

CHAPTER 3 CLOCK CONTROLLER
3.3 Registers
3.3.1

System Clock Control Register (SYCC)

The system clock control register (SYCC) selects a machine clock divide ratio
and a clock mode, and indicates the current clock mode.
■ Register Configuration
bit 7
Field SCM2
Attribute R
Initial value X
■ Register Functions
[bit7:5] SCM[2:0]: Clock mode monitor bits
These bits indicate the current clock mode.
These bits are read-only bits. Writing values to these bits has no effect on operation.
bit7:5
Reading "000"
Reading "010"
Reading "100"
Reading "110"
Reading "111"
[bit4:2] SCS[2:0]: Clock mode select bits
These bits select a clock mode.
bit4:2
Writing "000"
Writing "010"
Writing "100"
Writing "110"
Writing "111"
Note: Do not write to SCS[2:0] any value other than those listed in the table above.
[bit1:0] DIV[1:0]: Machine clock divide ratio select bits
These bits select the machine clock divide ratio for the source clock.
The machine clock is generated from the source clock according to the divide ratio set by these bits.
bit1:0
Writing "00"
Writing "01"
Writing "10"
Writing "11"
28
6 5
SCM1 SCM0
R R
X X
Indicates that the current clock mode is subclock mode.
Indicates that the current clock mode is main clock mode.
Indicates that the current clock mode is sub-CR clock mode.
Indicates that the current clock mode is main CR clock mode.
Indicates that the current clock mode is main CR PLL clock mode.
Selects subclock mode.
Selects main clock mode.
Selects sub-CR clock mode.
Selects main CR clock mode.
Selects main CR PLL clock mode.
Source clock (no division)
Source clock/4
Source clock/8
Source clock/16
FUJITSU SEMICONDUCTOR LIMITED
4 3
SCS2 SCS1
R/W R/W
1 1
Details
Details
Details
MB95630H Series
2 1
SCS0 DIV1
R/W R/W
0 1
MN702-00009-2v0-E
0
DIV0
R/W
1