Omron CJ - 09-2009 Operation Manual page 465

Auxiliary Area
Name Address
High-speed Counter A27510
1
Count Direction
High-speed Counter A53100
0 Reset Bit
High-speed Counter A53101
1 Reset Bit
High-speed Counter A53102
0 Gate Bit
High-speed Counter A53103
1 Gate Bit
Auxiliary Area Flags and Bits for Built-in Outputs
Name Address
Pulse Output 0 PV A276 to
A277
Pulse Output 1 PV A278 to
A279
Description
This flag indicates whether the high-speed
counter is currently being incremented or decre-
mented. The counter PV for the current cycle is
compared with the PV in last cycle to determine
the direction.
0: Decrementing
1: Incrementing
When the reset method is set to Phase-Z signal
+ Software reset, the corresponding high-speed
counter's PV will be reset if the phase-Z signal is
received while this bit is ON.
When the reset method is set to Software reset,
the corresponding high-speed counter's PV will
be reset in the cycle when this bit goes from
OFF to ON.
When a counter's Gate Bit is ON, the counter's
PV will not be changed even if pulse inputs are
received for the counter.
When the bit is turned OFF again, counting will
restart and the high-speed counter's PV will be
refreshed.
When the reset method is set to Phase-Z signal
+ Software reset, the Gate Bit is disabled while
the corresponding Reset Bit (A53100 or
A53101) is ON.
The following tables show the Auxiliary Area words and bits that are related to
the CJ1M CPU Unit's built-in outputs. These allocations apply to CPU Units
equipped with the built-in I/O only.
Description
Contain the number of pulses output from the
corresponding pulse output port.
PV range: 80000000 to 7FFFFFFF hex
(−2,147,483,648 to 2,147,483,647)
When pulses are being output in the CW direc-
tion, the PV is incremented by 1 for each pulse.
When pulses are being output in the CCW direc-
tion, the PV is decremented by 1 for each pulse.
PV after overflow: 7FFFFFFF hex
PV after underflow: 80000000 hex
A277 contains the leftmost 4 digits and A276
contains the rightmost 4 digits of the pulse out-
put 0 PV.
A279 contains the leftmost 4 digits and A278
contains the rightmost 4 digits of the pulse out-
put 1 PV.
Note If the coordinate system is relative coor-
dinates (undefined origin), the PV will be
cleared to 0 when a pulse output starts,
i.e. when a pulse output instruction
(SPED(885), ACC(888), or PLS2(887)) is
executed.
Section 9-11
Read/Write Times when data is
accessed
Read only • Setting used for
high-speed
counter, valid dur-
ing counter opera-
tion.
Read/Write • Cleared when
power is turned
ON.
Read/Write
Read/Write • Cleared when
power is turned
ON.
Read/Write
Read/Write Times when data is
accessed
Read only • Cleared when
power is turned
ON.
• Cleared when
operation starts.
• Refreshed each
cycle during over-
see process.
• Refreshed when
the INI(880)
instruction is exe-
cuted for the cor-
responding pulse
output.
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