Omron CJ - 09-2009 Operation Manual page 103

CJ1-H-R, CJ1-H, CJ1M, and CJ1 CPU Unit Comparison
Item
Execution CPU execution process-
timing ing modes
CPU Bus Data links
Unit spe-
DeviceNet
cial
remote I/O
refreshing
Protocol
macro
send/
receive
data
Refreshing of CIO and
DM Areas words allo-
cated to CPU Bus Unit
Tasks Cyclic execution of
interrupt tasks via
TKON instruction
(called "extra cyclic
tasks")
Independent/shared
specifications for index
and data registers
Initialization when tasks
are started
Starting subroutines
from multiple tasks
Scheduled interrupt
interval for scheduled
interrupt tasks
Interrupt For
task execu- instruc-
tion timing tions other
during than the
instruction following
execution ones
For BIT
COUNTE
R (BCNT)
or BLOCK
TRANS-
FER
(XFER)
instruc-
tions
Debug- Backup to Memory
ging Cards (simple backup
function)
Automatic user program
and parameter area
backup to flash memory
CJ1-H-R CPU
Unit
CJ1H-CPU6@H-R CJ1H-CPU6@H
Any of the following four modes:
1. Normal (instructions and peripheral servicing per-
formed consecutively)
2. Peripheral Servicing Priority Mode (instruction execu-
tion interrupted to service peripherals at a specific
cycle and time; consecutive refreshing also per-
formed)
3. Parallel Processing Mode with Synchronous Memory
Access (instruction executed and peripheral services
in parallel while synchronizing access to I/O memory)
4. Parallel Processing Mode with Asynchronous Memory
Access (instruction executed and peripheral services
in parallel without synchronizing access to I/O mem-
ory)
During I/O refresh period or via special CPU BUS UNIT I/O REFRESH instruc-
tion (DLNK(226))
Supported.
(Up to 256 extra cyclic tasks, increasing the total number of cyclic tasks to 288
max.)
Supported.
The time to switch between tasks can be reduced if shared registers are used.
Supported.
Task Startup Flags supported.
Global subroutines can be defined that can be called from more than one task.
0.2 ms to 999.9 ms 1 ms to 9,999 ms (in increments of
(in increments of 1 ms) or 10 ms to 99,990 ms (in
0.1 ms), 1 ms to increments of 10 ms)
9,999 ms (in incre-
ments of 1 ms), or
10 ms to 99,990
ms (in increments
of 10 ms)
Any instruction that is being executed is interrupted when interrupt task conditions are met to start
the interrupt task. If the cyclic task (including extra cyclic tasks) accesses the same data area
words as the instruction that was interrupted, data may not be concurrent. To ensure data concur-
rency, the DI and EI instructions must be used to disable and enable interrupts during a specific
part of the program.
Interrupt tasks are started only after execution of the instruction has been com-
pleted, ensuring data concurrency even when the same data area words are
accessed from the instruction and the interrupt task.
In addition to the data listed at the right, data from Units mounted to the CPU
Rack or Expansion Racks can also be backed up to the Memory Card (via push-
button on front panel). This is very effective when replacing Units. Backup data
includes scan lists for DeviceNet Units, protocol macros for Serial Communica-
tions Units, etc.
Supported (enabling battery-free operation without a Memory Card)
The user program and parameter area data are automatically backed up the
flash memory whenever they are transferred to the CPU Unit from the CX-Pro-
grammer, file memory, etc.
CJ1-H CPU Unit
CJ1G-CPU4@H CJ1M-CPU2@/1@
Either of following two modes:
1. Either of following two modes: Normal
2. Peripheral Servicing Priority Mode
0.5 ms to 999.9 ms
(in increments of
0.1 ms), 1 ms to
9,999 ms (in incre-
ments of 1 ms), or
10 ms to 99,990 ms
(in increments of
10 ms)
Section 1-7
CJ1M CPU Unit CJ1 CPU Unit
CJ1G-CPU4@
(instructions and peripheral servicing
performed consecutively)
(instruction execution interrupted to
service peripherals at a specific cycle
and time; consecutive refreshing also
performed)
During I/O
refresh period
Not supported.
(No extra cyclic
tasks; 32 cyclic
tasks max.)
Not supported.
(Only indepen-
dent registers for
each task.)
Only Task Flag
for first execu-
tion.
Not supported.
1 ms to 9,999 ms
(in increments of
1 ms) or 10 ms
to 99,990 ms (in
increments of
10 ms)
Only the user
program, param-
eters, and I/O
memory in the
CPU Unit.
Not supported.
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