Xilinx VCU1287 User Manual page 78

Characterization board
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set_property PACKAGE_PIN AT11
set_property PACKAGE_PIN AT10
set_property PACKAGE_PIN AP7
set_property PACKAGE_PIN AP6
set_property PACKAGE_PIN AP2
set_property PACKAGE_PIN AP1
set_property PACKAGE_PIN AR9
set_property PACKAGE_PIN AR8
set_property PACKAGE_PIN AR4
set_property PACKAGE_PIN AR3
set_property PACKAGE_PIN AT7
set_property PACKAGE_PIN AT6
set_property PACKAGE_PIN AT2
set_property PACKAGE_PIN AT1
set_property PACKAGE_PIN AU9
set_property PACKAGE_PIN AU8
set_property PACKAGE_PIN AU4
set_property PACKAGE_PIN AU3
set_property PACKAGE_PIN AK11
set_property PACKAGE_PIN AK10
set_property PACKAGE_PIN AM11
set_property PACKAGE_PIN AM10
set_property PACKAGE_PIN AK7
set_property PACKAGE_PIN AK6
set_property PACKAGE_PIN AK2
set_property PACKAGE_PIN AK1
set_property PACKAGE_PIN AL9
set_property PACKAGE_PIN AL8
set_property PACKAGE_PIN AL4
set_property PACKAGE_PIN AL3
set_property PACKAGE_PIN AM7
set_property PACKAGE_PIN AM6
set_property PACKAGE_PIN AM2
set_property PACKAGE_PIN AM1
set_property PACKAGE_PIN AN9
set_property PACKAGE_PIN AN8
set_property PACKAGE_PIN AN4
set_property PACKAGE_PIN AN3
set_property PACKAGE_PIN AF11
set_property PACKAGE_PIN AF10
set_property PACKAGE_PIN AH11
set_property PACKAGE_PIN AH10
set_property PACKAGE_PIN AF7
set_property PACKAGE_PIN AF6
set_property PACKAGE_PIN AF2
set_property PACKAGE_PIN AF1
set_property PACKAGE_PIN AG9
set_property PACKAGE_PIN AG8
set_property PACKAGE_PIN AG4
set_property PACKAGE_PIN AG3
set_property PACKAGE_PIN AH7
set_property PACKAGE_PIN AH6
set_property PACKAGE_PIN AH2
set_property PACKAGE_PIN AH1
set_property PACKAGE_PIN AJ9
set_property PACKAGE_PIN AJ8
set_property PACKAGE_PIN AJ4
set_property PACKAGE_PIN AJ3
set_property PACKAGE_PIN AB11
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Appendix Appendix C:
[get_ports "225_REFCLK0_P"]
[get_ports "225_REFCLK0_N"]
[get_ports "225_TX3_P"]
[get_ports "225_TX3_N"]
[get_ports "225_RX3_P"]
[get_ports "225_RX3_N"]
[get_ports "225_TX2_P"]
[get_ports "225_TX2_N"]
[get_ports "225_RX2_P"]
[get_ports "225_RX2_N"]
[get_ports "225_TX1_P"]
[get_ports "225_TX1_N"]
[get_ports "225_RX1_P"]
[get_ports "225_RX1_N"]
[get_ports "225_TX0_P"]
[get_ports "225_TX0_N"]
[get_ports "225_RX0_P"]
[get_ports "225_RX0_N"]
[get_ports "226_REFCLK1_P"]
[get_ports "226_REFCLK1_N"]
[get_ports "226_REFCLK0_P"]
[get_ports "226_REFCLK0_N"]
[get_ports "226_TX3_P"]
[get_ports "226_TX3_N"]
[get_ports "226_RX3_P"]
[get_ports "226_RX3_N"]
[get_ports "226_TX2_P"]
[get_ports "226_TX2_N"]
[get_ports "226_RX2_P"]
[get_ports "226_RX2_N"]
[get_ports "226_TX1_P"]
[get_ports "226_TX1_N"]
[get_ports "226_RX1_P"]
[get_ports "226_RX1_N"]
[get_ports "226_TX0_P"]
[get_ports "226_TX0_N"]
[get_ports "226_RX0_P"]
[get_ports "226_RX0_N"]
[get_ports "227_REFCLK1_P"]
[get_ports "227_REFCLK1_N"]
[get_ports "227_REFCLK0_P"]
[get_ports "227_REFCLK0_N"]
[get_ports "227_TX3_P"]
[get_ports "227_TX3_N"]
[get_ports "227_RX3_P"]
[get_ports "227_RX3_N"]
[get_ports "227_TX2_P"]
[get_ports "227_TX2_N"]
[get_ports "227_RX2_P"]
[get_ports "227_RX2_N"]
[get_ports "227_TX1_P"]
[get_ports "227_TX1_N"]
[get_ports "227_RX1_P"]
[get_ports "227_RX1_N"]
[get_ports "227_TX0_P"]
[get_ports "227_TX0_N"]
[get_ports "227_RX0_P"]
[get_ports "227_RX0_N"]
[get_ports "228_REFCLK1_P"]
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