Xilinx VCU1287 User Manual page 72

Characterization board
Hide thumbs Also See for VCU1287:
Table of Contents

Advertisement

set_property PACKAGE_PIN BE35
set_property IOSTANDARD
set_property PACKAGE_PIN BC34
set_property IOSTANDARD
set_property PACKAGE_PIN BD34
set_property IOSTANDARD
set_property PACKAGE_PIN BA35
set_property IOSTANDARD
set_property PACKAGE_PIN BB35
set_property IOSTANDARD
set_property PACKAGE_PIN BB38
set_property IOSTANDARD
set_property PACKAGE_PIN BC38
set_property IOSTANDARD
set_property PACKAGE_PIN BC39
set_property IOSTANDARD
set_property PACKAGE_PIN BD39
set_property IOSTANDARD
set_property PACKAGE_PIN BD40
set_property IOSTANDARD
set_property PACKAGE_PIN BE40
set_property IOSTANDARD
set_property PACKAGE_PIN BE37
set_property IOSTANDARD
set_property PACKAGE_PIN BF37
set_property IOSTANDARD
#SUPERCLOCK-2 MODULE
set_property PACKAGE_PIN C28
set_property IOSTANDARD
set_property PACKAGE_PIN D29
set_property IOSTANDARD
set_property PACKAGE_PIN C29
set_property IOSTANDARD
set_property PACKAGE_PIN C27
set_property IOSTANDARD
set_property PACKAGE_PIN B27
set_property IOSTANDARD
set_property PACKAGE_PIN A28
set_property IOSTANDARD
set_property PACKAGE_PIN E30
set_property IOSTANDARD
set_property PACKAGE_PIN D30
set_property IOSTANDARD
set_property PACKAGE_PIN B30
set_property IOSTANDARD
set_property PACKAGE_PIN A30
set_property IOSTANDARD
set_property PACKAGE_PIN B29
set_property IOSTANDARD
set_property PACKAGE_PIN A29
set_property IOSTANDARD
set_property PACKAGE_PIN A27
set_property IOSTANDARD
set_property PACKAGE_PIN L13
set_property IOSTANDARD
set_property PACKAGE_PIN K13
set_property IOSTANDARD
set_property PACKAGE_PIN J33
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Appendix Appendix C:
[get_ports "FMC3_HB15N"]
LVCMOS18 [get_ports "FMC3_HB15N"]
[get_ports "FMC3_HB16P"]
LVCMOS18 [get_ports "FMC3_HB16P"]
[get_ports "FMC3_HB16N"]
LVCMOS18 [get_ports "FMC3_HB16N"]
[get_ports "FMC3_HB17_CC_P"]
LVCMOS18 [get_ports "FMC3_HB17_CC_P"]
[get_ports "FMC3_HB17_CC_N"]
LVCMOS18 [get_ports "FMC3_HB17_CC_N"]
[get_ports "FMC3_HB18P"]
LVCMOS18 [get_ports "FMC3_HB18P"]
[get_ports "FMC3_HB18N"]
LVCMOS18 [get_ports "FMC3_HB18N"]
[get_ports "FMC3_HB19P"]
LVCMOS18 [get_ports "FMC3_HB19P"]
[get_ports "FMC3_HB19N"]
LVCMOS18 [get_ports "FMC3_HB19N"]
[get_ports "FMC3_HB20P"]
LVCMOS18 [get_ports "FMC3_HB20P"]
[get_ports "FMC3_HB20N"]
LVCMOS18 [get_ports "FMC3_HB20N"]
[get_ports "FMC3_HB21P"]
LVCMOS18 [get_ports "FMC3_HB21P"]
[get_ports "FMC3_HB21N"]
LVCMOS18 [get_ports "FMC3_HB21N"]
[get_ports "CM_RST_B"]
LVCMOS18 [get_ports "CM_RST_B"]
[get_ports "CM_C1A"]
LVCMOS18 [get_ports "CM_C1A"]
[get_ports "CM_C2A"]
LVCMOS18 [get_ports "CM_C2A"]
[get_ports "CM_H_CS0_C3A"]
LVCMOS18 [get_ports "CM_H_CS0_C3A"]
[get_ports "CM_H_CS1_C4A"]
LVCMOS18 [get_ports "CM_H_CS1_C4A"]
[get_ports "CM_C1B"]
LVCMOS18 [get_ports "CM_C1B"]
[get_ports "CM_C2B"]
LVCMOS18 [get_ports "CM_C2B"]
[get_ports "CM_C3B"]
LVCMOS18 [get_ports "CM_C3B"]
[get_ports "CM_H_DEC"]
LVCMOS18 [get_ports "CM_H_DEC"]
[get_ports "CM_H_INC"]
LVCMOS18 [get_ports "CM_H_INC"]
[get_ports "CM_FS_ALIGN"]
LVCMOS18 [get_ports "CM_FS_ALIGN"]
[get_ports "CM_H_LOL"]
LVCMOS18 [get_ports "CM_H_LOL"]
[get_ports "CM_H_INT_ALRM"]
LVCMOS18 [get_ports "CM_H_INT_ALRM"]
[get_ports "CM_LVDS1_P"]
LVCMOS18 [get_ports "CM_LVDS1_P"]
[get_ports "CM_LVDS1_N"]
LVCMOS18 [get_ports "CM_LVDS1_N"]
[get_ports "CM_LVDS2_P"]
www.xilinx.com
Master Constraints File Listing
Send Feedback
72

Advertisement

Table of Contents
loading

Table of Contents