Xilinx Virtex-4 QV FPGA Manual
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Xilinx Virtex-4 QV FPGA Manual

Xilinx Virtex-4 QV FPGA Manual

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Virtex-4 QV
Virtex-4 QV FPGA
FPGA Ceramic
Ceramic Packaging and
Packaging and
Pinout Specifications
[Guide Subtitle]
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UG496 (v1.1) June 8, 2012 [optional]
UG496 (v1.1) June 8, 2012
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Summary of Contents for Xilinx Virtex-4 QV FPGA

  • Page 1 Virtex-4 QV Virtex-4 QV FPGA FPGA Ceramic Ceramic Packaging and Packaging and Pinout Specifications [Guide Subtitle] [optional] UG496 (v1.1) June 8, 2012 [optional] UG496 (v1.1) June 8, 2012...

  • Page 2: Revision History

    Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Table Of Contents

    ........176 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com...
  • Page 4 Chapter 6: Guidelines for Xilinx CF Package Handling and Assembly Product Unpacking ............177 Product Handling and Inspection .

  • Page 5: Preface: About This Guide

    Radiation-Hardened FPGAs. • Chapter 5, “Thermal Specifications,” provides thermal data associated with Virtex-4 QV Radiation-Hardened FPGA packaging. Discusses Virtex-4 QV FPGA power management strategy and thermal management options. Additional Resources To find additional documentation, see the Xilinx website at: http://www.xilinx.com/literature.

  • Page 6: Conventions

    IOB #2: Name = CLKIN’ Repetitive material that has been omitted Repetitive material that has allow block block_name loc1 Horizontal ellipsis . . . been omitted loc2 ... locn; www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 7: Online Document

    Figure 2-5 in the Virtex-II Red text in another document Platform FPGA User Guide. Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 8 Preface: About This Guide www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 9: Chapter 1: Device Packaging Overview

    FPGA. The number of I/Os per package includes all user I/Os except the fifteen control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO, TMS, HSWAPEN, DXN, DXP, AND RSVD). Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...

  • Page 10: Pin Definitions

    Pin Definitions Table 1-3 provides a description of each pin type listed in Virtex-4 QV FPGA pinout tables. The "_#" suffix appended to some pin descriptions indicates the bank in which that pin resides. Pins without this suffix appended are not associated with any particular bank.
  • Page 11 High, which is its default state. It does not require an external pull-up. Do not connect this pin—leave floating. RDWR_B_0 Input In SelectMAP mode, this is the active-low Write Enable signal. TCK_0 Input Boundary-Scan Clock TDI_0 Input Boundary-Scan Data Input Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 12 AVCCAUXMGT_# Input Analog power supply for global bias (2.5V). GNDA_# Input Ground for the analog circuitry of the RocketIO MGT. MGTCLK_# Input Differential reference clock for the RocketIO MGT. www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 13 2. For more information on lower capacitance pins, see the UG070, Virtex-4 User Guide. 3. For more information on RocketIO pins, see the UG076, Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide. Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 14 Chapter 1: Device Packaging Overview www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 15: Chapter 2: Pinout Tables

    Note: Check www.xilinx.com for the latest pinout information. ASCII package pinout files are also available for download from the Xilinx website. CF1140 (SX55) Ceramic Flip-Chip Column Grid Package As shown in Table 2-1, the Virtex-4 QV XQR4VSX55 FPGA is available in the CF1140 ceramic flip-chip column grid package.
  • Page 16 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 IO_L7P_D19_LC_1 IO_L7N_D18_LC_1 IO_L8P_D17_CC_LC_1 IO_L8N_D16_CC_LC_1 IO_L9P_GC_LC_1 IO_L9N_GC_LC_1 IO_L10P_GC_LC_1 IO_L10N_GC_LC_1 IO_L11P_GC_LC_1 IO_L11N_GC_LC_1 IO_L12P_GC_LC_1 IO_L12N_GC_VREF_LC_1 IO_L13P_GC_LC_1 IO_L13N_GC_LC_1 IO_L14P_GC_LC_1 IO_L14N_GC_LC_1 IO_L15P_GC_LC_1 IO_L15N_GC_LC_1 IO_L16P_GC_CC_LC_1 IO_L16N_GC_CC_LC_1 IO_L17P_CC_LC_1 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 17 AL14 IO_L4N_D8_VREF_LC_2 AK14 IO_L5P_D7_LC_2 AG21 IO_L5N_D6_LC_2 AF20 IO_L6P_D5_LC_2 AF14 IO_L6N_D4_LC_2 AG13 IO_L7P_D3_LC_2 AE21 IO_L7N_D2_LC_2 AF21 IO_L8P_D1_LC_2 AP15 IO_L8N_D0_LC_2 AN15 IO_L9P_GC_CC_LC_2 AC19 IO_L9N_GC_CC_LC_2 AB18 IO_L10P_GC_LC_2 AD16 IO_L10N_GC_LC_2 AF15 IO_L11P_GC_LC_2 AN20 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 18 IO_L20P_LC_2 AJ15 IO_L20N_VREF_LC_2 AJ14 IO_L21P_LC_2 AG20 IO_L21N_LC_2 AH20 IO_L22P_LC_2 AG15 IO_L22N_LC_2 AH14 IO_L23P_VRN_LC_2 AD19 IO_L23N_VRP_LC_2 AE19 IO_L24P_CC_LC_2 AL16 IO_L24N_CC_LC_2 AK16 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 19 AK17 IO_L5P_GC_LC_4 AG18 IO_L5N_GC_LC_4 AG17 IO_L6P_GC_LC_4 AE17 IO_L6N_GC_LC_4 AE16 IO_L7P_GC_VRN_LC_4 AJ19 IO_L7N_GC_VRP_LC_4 AK19 IO_L8P_GC_CC_LC_4 AJ17 IO_L8N_GC_CC_LC_4 AH17 IO_L1P_ADC7_5 IO_L1N_ADC7_5 IO_L2P_ADC6_5 IO_L2N_ADC6_5 IO_L3P_ADC5_5 IO_L3N_ADC5_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_ADC4_5 IO_L5N_ADC4_5 IO_L6P_ADC3_5 IO_L6N_ADC3_5 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 20 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 21 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 22 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 23 AP22 IO_L18P_7 AP29 IO_L18N_7 AN29 IO_L19P_7 AK24 IO_L19N_7 AJ24 IO_L20P_7 AK27 IO_L20N_VREF_7 AK28 IO_L21P_7 AG23 IO_L21N_7 AF24 IO_L22P_7 AG25 IO_L22N_7 AG26 IO_L23P_VRN_7 AH23 IO_L23N_VRP_7 AH24 IO_L24P_CC_LC_7 AN28 IO_L24N_CC_LC_7 AM28 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 24 AN27 IO_L12P_7 AP31 IO_L12N_VREF_7 AP32 IO_L13P_7 AK22 IO_L13N_7 AK23 IO_L14P_7 AL28 IO_L14N_7 AL29 IO_L15P_7 AP25 IO_L15N_7 AP26 IO_L16P_7 AJ27 IO_L16N_7 AH27 IO_L25P_CC_LC_8 AL11 IO_L25N_CC_LC_8 AL10 IO_L26P_8 AE11 IO_L26N_8 AF11 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 25 AM10 IO_L20P_8 AF10 IO_L20N_VREF_8 IO_L21P_8 AJ12 IO_L21N_8 AK12 IO_L22P_8 IO_L22N_8 IO_L23P_VRN_8 AJ11 IO_L23N_VRP_8 AK11 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L1P_8 IO_L1N_8 IO_L2P_8 IO_L2N_8 IO_L3P_8 IO_L3N_8 IO_L4P_8 AD10 IO_L4N_VREF_8 IO_L5P_8 AN14 IO_L5N_8 AP14 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 26 IO_L11P_8 IO_L11N_8 IO_L12P_8 IO_L12N_VREF_8 IO_L13P_8 AM13 IO_L13N_8 AN13 IO_L14P_8 IO_L14N_8 IO_L15P_8 AJ10 IO_L15N_8 IO_L16P_8 IO_L16N_8 IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 27 IO_L4N_VREF_9 IO_L5P_9 IO_L5N_9 IO_L6P_9 IO_L6N_9 IO_L7P_9 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 IO_L12P_9 IO_L12N_VREF_9 IO_L13P_9 IO_L13N_9 IO_L14P_9 IO_L14N_9 IO_L15P_9 IO_L15N_9 IO_L16P_9 IO_L16N_9 IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 IO_L26P_9 IO_L26N_9 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 28 IO_L30N_9 IO_L31P_9 IO_L31N_9 IO_L32P_9 IO_L32N_9 IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 IO_L1P_10 IO_L1N_10 IO_L2P_10 IO_L2N_10 IO_L3P_10 IO_L3N_10 IO_L4P_10 IO_L4N_VREF_10 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 29 IO_L9N_CC_LC_10 IO_L10P_10 IO_L10N_10 IO_L11P_10 IO_L11N_10 IO_L12P_10 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 IO_L25N_CC_LC_10 IO_L26P_10 IO_L26N_10 IO_L27P_10 IO_L27N_10 IO_L28P_10 IO_L28N_VREF_10 IO_L29P_10 IO_L29N_10 IO_L30P_10 IO_L30N_10 IO_L31P_10 IO_L31N_10 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 30 AA29 IO_L2P_11 IO_L2N_11 IO_L3P_11 AB30 IO_L3N_11 AA30 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 AE33 IO_L5N_11 AE34 IO_L6P_11 AC32 IO_L6N_11 AC33 IO_L7P_11 AC29 IO_L7N_11 AC30 IO_L8P_CC_LC_11 AD34 IO_L8N_CC_LC_11 AC34 IO_L9P_CC_LC_11 AA25 IO_L9N_CC_LC_11 AA26 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 31 AM32 IO_L27N_11 AM33 IO_L28P_11 AJ31 IO_L28N_VREF_11 AJ32 IO_L29P_11 AB22 IO_L29N_11 AB23 IO_L30P_11 AL33 IO_L30N_11 AL34 IO_L31P_11 AM31 IO_L31N_11 AL31 IO_L32P_11 AJ30 IO_L32N_11 AH30 IO_L17P_12 IO_L17N_12 IO_L18P_12 IO_L18N_12 IO_L19P_12 IO_L19N_12 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 32 IO_L2P_12 IO_L2N_12 IO_L3P_12 IO_L3N_12 AA11 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 AA13 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12 IO_L8P_CC_LC_12 IO_L8N_CC_LC_12 IO_L9P_CC_LC_12 IO_L9N_CC_LC_12 IO_L10P_12 IO_L10N_12 IO_L11P_12 IO_L11N_12 IO_L12P_12 IO_L12N_VREF_12 IO_L13P_12 IO_L13N_12 AA15 IO_L14P_12 IO_L14N_12 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 33 IO_L27N_12 IO_L28P_12 IO_L28N_VREF_12 IO_L29P_12 AB13 IO_L29N_12 AB12 IO_L30P_12 IO_L30N_12 IO_L31P_12 IO_L31N_12 IO_L32P_12 IO_L32N_12 IO_L17P_13 IO_L17N_13 IO_L18P_13 IO_L18N_13 IO_L19P_13 IO_L19N_13 IO_L20P_13 IO_L20N_VREF_13 IO_L21P_13 IO_L21N_13 IO_L22P_13 IO_L22N_13 IO_L23P_VRN_13 IO_L23N_VRP_13 IO_L24P_CC_LC_13 IO_L24N_CC_LC_13 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 34 IO_L5N_13 IO_L6P_13 IO_L6N_13 IO_L7P_13 IO_L7N_13 IO_L8P_CC_LC_13 IO_L8N_CC_LC_13 IO_L9P_CC_LC_13 IO_L9N_CC_LC_13 IO_L10P_13 IO_L10N_13 IO_L11P_13 IO_L11N_13 IO_L12P_13 IO_L12N_VREF_13 IO_L13P_13 IO_L13N_13 IO_L14P_13 IO_L14N_13 IO_L15P_13 IO_L15N_13 IO_L16P_13 IO_L16N_13 IO_L25P_CC_LC_13 IO_L25N_CC_LC_13 IO_L26P_13 IO_L26N_13 IO_L27P_13 IO_L27N_13 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 35 AA31 IO_L32P_13 IO_L32N_13 IO_L17P_14 IO_L17N_14 IO_L18P_14 IO_L18N_14 IO_L19P_14 IO_L19N_14 IO_L20P_14 IO_L20N_VREF_14 IO_L21P_14 IO_L21N_14 IO_L22P_14 IO_L22N_14 IO_L23P_VRN_14 IO_L23N_VRP_14 IO_L24P_CC_LC_14 IO_L24N_CC_LC_14 IO_L1P_14 IO_L1N_14 IO_L2P_14 IO_L2N_14 IO_L3P_14 IO_L3N_14 IO_L4P_14 IO_L4N_VREF_14 IO_L5P_14 IO_L5N_14 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 36 IO_L10N_14 IO_L11P_14 IO_L11N_14 IO_L12P_14 IO_L12N_VREF_14 IO_L13P_14 IO_L13N_14 IO_L14P_14 IO_L14N_14 IO_L15P_14 IO_L15N_14 IO_L16P_14 IO_L16N_14 IO_L25P_CC_LC_14 IO_L25N_CC_LC_14 IO_L26P_14 IO_L26N_14 IO_L27P_14 IO_L27N_14 IO_L28P_14 IO_L28N_VREF_14 IO_L29P_14 IO_L29N_14 IO_L30P_14 IO_L30N_14 IO_L31P_14 IO_L31N_14 IO_L32P_14 IO_L32N_14 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 37 AC16 VCCO_2 AN16 VCCO_2 AB19 VCCO_2 AM19 VCCO_2 AE20 VCCO_2 AH21 VCCO_3 VCCO_3 VCCO_4 AF17 VCCO_4 AJ18 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 38 VCCO_7 AP33 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 VCCO_8 AE10 VCCO_8 AH11 VCCO_8 AL12 VCCO_8 AP13 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 39 VCCO_11 AG34 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 AA12 VCCO_12 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 AA32 VCCO_13 VCCO_13 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 40 Table 2-1: CF1140 Package Pinout (SX55) (Cont’d) Bank Pin Description No Connects Number VREFN_SM AN17 VREFP_SM AN18 AVDD_SM AP19 VN_SM AP17 VP_SM AP18 AVSS_SM AN19 VREFN_ADC VREFP_ADC AVDD_ADC VN_ADC VP_ADC AVSS_ADC www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 41 CF1140 (SX55) Ceramic Flip-Chip Column Grid Package Table 2-1: CF1140 Package Pinout (SX55) (Cont’d) Bank Pin Description No Connects Number AK10 AC11 AN11 AD12 AF12 AC13 AE13 AJ13 AB14 AD14 AM14 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 42 Chapter 2: Pinout Tables Table 2-1: CF1140 Package Pinout (SX55) (Cont’d) Bank Pin Description No Connects Number AE15 AH16 AP16 AA17 AL17 AD18 AA19 AG19 AB20 AK20 AC21 AN21 AD22 AF22 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 43 Table 2-1: CF1140 Package Pinout (SX55) (Cont’d) Bank Pin Description No Connects Number AC23 AE23 AJ23 AB24 AD24 AM24 AE25 AH26 AA27 AL27 AD28 AP28 AG29 AK30 AC31 AN31 AF32 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 44 VCCAUX VCCAUX AD11 VCCAUX AG12 VCCAUX VCCAUX AJ16 VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX AC24 VCCAUX VCCAUX AF25 VCCAUX VCCAUX VCCAUX AJ26 VCCAUX AB27 VCCINT VCCINT VCCINT VCCINT www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 45 AC14 VCCINT AE14 VCCINT VCCINT VCCINT VCCINT VCCINT AD15 VCCINT AH15 VCCINT VCCINT VCCINT VCCINT AA16 VCCINT VCCINT VCCINT VCCINT AA18 VCCINT AC18 VCCINT VCCINT VCCINT VCCINT AF19 VCCINT Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 46 Virtex-4 Configuration Guide. CC_CONFIG 2. Connect this reserved pin to GND. 3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V is acceptable). CCAUX www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 47: Cf1144 (Fx60) Ceramic Flip-Chip Column Grid Package

    DONE_0 RDWR_B_0 VBATT_0 M2_0 PWRDWN_B_0 AA16 TMS_0 M0_0 TDO_0 TCK_0 AA14 M1_0 DOUT_BUSY_0 TDI_0 AA15 TDN_0 TDP_0 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 48 IO_L5N_D6_LC_2 AJ20 IO_L6P_D5_LC_2 AJ19 IO_L6N_D4_LC_2 AK19 IO_L7P_D3_LC_2 AG20 IO_L7N_D2_LC_2 AH20 IO_L8P_D1_LC_2 AH19 IO_L8N_D0_LC_2 AH18 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 IO_L2P_GC_VRN_LC_3 IO_L2N_GC_VRP_LC_3 IO_L3P_GC_LC_3 IO_L3N_GC_LC_3 IO_L4P_GC_LC_3 IO_L4N_GC_VREF_LC_3 IO_L5P_GC_LC_3 IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 49 AG17 IO_L6N_GC_LC_4 AG16 IO_L7P_GC_VRN_LC_4 AD19 IO_L7N_GC_VRP_LC_4 AE19 IO_L8P_GC_CC_LC_4 AF18 IO_L8N_GC_CC_LC_4 AG18 IO_L1P_ADC7_5 IO_L1N_ADC7_5 IO_L2P_ADC6_5 IO_L2N_ADC6_5 IO_L3P_ADC5_5 IO_L3N_ADC5_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_ADC4_5 IO_L5N_ADC4_5 IO_L6P_ADC3_5 IO_L6N_ADC3_5 IO_L7P_ADC2_5 IO_L7N_ADC2_5 IO_L8P_CC_ADC1_LC_5 IO_L8N_CC_ADC1_LC_5 IO_L17P_5 IO_L17N_5 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 50 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 51 IO_L32N_5 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 52 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 IO_L28N_VREF_6 IO_L29P_6 IO_L29N_6 IO_L30P_6 IO_L30N_6 IO_L31P_6 IO_L31N_6 IO_L32P_6 IO_L32N_6 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 53 AE23 IO_L21P_7 AE27 IO_L21N_7 AE26 IO_L22P_7 AL24 IO_L22N_7 AK24 IO_L23P_VRN_7 AK27 IO_L23N_VRP_7 AK26 IO_L24P_CC_LC_7 AJ24 IO_L24N_CC_LC_7 AH24 IO_L1P_7 AK32 IO_L1N_7 AK31 IO_L2P_7 AL19 IO_L2N_7 AL18 IO_L3P_7 AM32 IO_L3N_7 AM31 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 54 AM23 IO_L14N_7 AL23 IO_L15P_7 AK28 IO_L15N_7 AL28 IO_L16P_7 AK23 IO_L16N_7 AK22 IO_L25P_CC_LC_8 AG13 IO_L25N_CC_LC_8 AH13 IO_L26P_8 AJ12 IO_L26N_8 AK12 IO_L27P_8 AF11 IO_L27N_8 AG11 IO_L28P_8 IO_L28N_VREF_8 IO_L29P_8 AG12 IO_L29N_8 AH12 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 55 AJ14 IO_L24P_CC_LC_8 AJ11 IO_L24N_CC_LC_8 AK11 IO_L1P_8 AB11 IO_L1N_8 AA11 IO_L2P_8 IO_L2N_8 IO_L3P_8 AB13 IO_L3N_8 AA13 IO_L4P_8 IO_L4N_VREF_8 IO_L5P_8 AC12 IO_L5N_8 AB12 IO_L6P_8 IO_L6N_8 IO_L7P_8 AD14 IO_L7N_8 AC13 IO_L8P_CC_LC_8 IO_L8N_CC_LC_8 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 56 IO_L14N_8 IO_L15P_8 AE13 IO_L15N_8 AF13 IO_L16P_8 AL10 IO_L16N_8 AM10 IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9 IO_L24P_CC_LC_9 IO_L24N_CC_LC_9 IO_L1P_9 IO_L1N_9 IO_L2P_9 IO_L2N_9 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 57 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 IO_L12P_9 IO_L12N_VREF_9 IO_L13P_9 IO_L13N_9 IO_L14P_9 IO_L14N_9 IO_L15P_9 IO_L15N_9 IO_L16P_9 IO_L16N_9 IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 IO_L26P_9 IO_L26N_9 IO_L27P_9 IO_L27N_9 IO_L28P_9 IO_L28N_VREF_9 IO_L29P_9 IO_L29N_9 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 58 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 IO_L1P_10 IO_L1N_10 IO_L2P_10 IO_L2N_10 IO_L3P_10 IO_L3N_10 IO_L4P_10 IO_L4N_VREF_10 IO_L5P_10 IO_L5N_10 IO_L6P_10 IO_L6N_10 IO_L7P_10 IO_L7N_10 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 59 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 IO_L25N_CC_LC_10 IO_L26P_10 IO_L26N_10 IO_L27P_10 IO_L27N_10 IO_L28P_10 IO_L28N_VREF_10 IO_L29P_10 IO_L29N_10 IO_L30P_10 IO_L30N_10 IO_L31P_10 IO_L31N_10 IO_L32P_10 IO_L32N_10 IO_L17P_11 AA26 IO_L17N_11 AA25 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 60 IO_L24P_CC_LC_11 AG32 IO_L24N_CC_LC_11 AH32 IO_L1P_11 IO_L1N_11 IO_L2P_11 IO_L2N_11 IO_L3P_11 IO_L3N_11 IO_L4P_11 IO_L4N_VREF_11 IO_L5P_11 IO_L5N_11 IO_L6P_11 IO_L6N_11 IO_L7P_11 IO_L7N_11 IO_L8P_CC_LC_11 IO_L8N_CC_LC_11 IO_L9P_CC_LC_11 IO_L9N_CC_LC_11 IO_L10P_11 IO_L10N_11 IO_L11P_11 IO_L11N_11 IO_L12P_11 IO_L12N_VREF_11 AA24 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 61 AD25 IO_L29P_11 AE29 IO_L29N_11 AF29 IO_L30P_11 AJ32 IO_L30N_11 AJ31 IO_L31P_11 AG31 IO_L31N_11 AG30 IO_L32P_11 AH30 IO_L32N_11 AJ30 IO_L17P_12 IO_L17N_12 IO_L18P_12 IO_L18N_12 IO_L19P_12 IO_L19N_12 IO_L20P_12 IO_L20N_VREF_12 IO_L21P_12 IO_L21N_12 IO_L22P_12 IO_L22N_12 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 62 IO_L3N_12 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12 IO_L8P_CC_LC_12 IO_L8N_CC_LC_12 IO_L9P_CC_LC_12 IO_L9N_CC_LC_12 IO_L10P_12 IO_L10N_12 IO_L11P_12 IO_L11N_12 IO_L12P_12 IO_L12N_VREF_12 IO_L13P_12 IO_L13N_12 IO_L14P_12 IO_L14N_12 IO_L15P_12 IO_L15N_12 IO_L16P_12 IO_L16N_12 IO_L25P_CC_LC_12 IO_L25N_CC_LC_12 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 63 IO_L31N_12 IO_L32P_12 IO_L32N_12 VCCO_0 VCCO_0 VCCO_0 VCCO_0 VCCO_1 VCCO_1 VCCO_2 AJ18 VCCO_2 AH21 VCCO_3 VCCO_3 VCCO_4 AF17 VCCO_4 AE20 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 64 AL32 VCCO_8 VCCO_8 VCCO_8 AE10 VCCO_8 AH11 VCCO_8 AA12 VCCO_8 AL12 VCCO_8 AD13 VCCO_8 AG14 VCCO_8 AK15 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_10 VCCO_10 VCCO_10 VCCO_10 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 65 VCCO_11 VCCO_11 AH31 VCCO_11 AA32 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 AVCCAUXRXA_101 RXPPADA_101 VTRXA_101 RXNPADA_101 AVCCAUXMGT_101 AVCCAUXTX_101 VTTXA_101 TXPPADA_101 TXNPADA_101 VTTXB_101 TXPPADB_101 TXNPADB_101 AVCCAUXRXB_101 RXPPADB_101 VTRXB_101 RXNPADB_101 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 66 AVCCAUXRXB_102 RXPPADB_102 VTRXB_102 RXNPADB_102 MGTCLK_P_102 MGTCLK_N_102 AVCCAUXRXA_103 RXPPADA_103 VTRXA_103 RXNPADA_103 AVCCAUXMGT_103 AC33 AVCCAUXTX_103 VTTXA_103 TXPPADA_103 TXNPADA_103 VTTXB_103 AA33 TXPPADB_103 TXNPADB_103 AA34 AVCCAUXRXB_103 AE33 RXPPADB_103 AC34 VTRXB_103 AB34 RXNPADB_103 AD34 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 67 AP26 VTRXA_106 AP24 RXNPADA_106 AP25 AVCCAUXMGT_106 AN18 AVCCAUXTX_106 AN22 VTTXA_106 AN23 TXPPADA_106 AP23 TXNPADA_106 AP22 VTTXB_106 AN20 TXPPADB_106 AP21 TXNPADB_106 AP20 AVCCAUXRXB_106 AN17 RXPPADB_106 AP18 VTRXB_106 AP19 RXNPADB_106 AP17 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 68 TXNPADB_109 AP12 AVCCAUXRXB_109 AN15 RXPPADB_109 AP14 VTRXB_109 AP13 RXNPADB_109 AP15 AVCCAUXRXA_110 RXPPADA_110 VTRXA_110 RXNPADA_110 AVCCAUXMGT_110 AVCCAUXTX_110 VTTXA_110 TXPPADA_110 TXNPADA_110 VTTXB_110 TXPPADB_110 TXNPADB_110 AVCCAUXRXB_110 RXPPADB_110 VTRXB_110 RXNPADB_110 MGTCLK_P_110 MGTCLK_N_110 RTERM_110 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 69 AVCCAUXTX_112 VTTXA_112 TXPPADA_112 TXNPADA_112 VTTXB_112 TXPPADB_112 TXNPADB_112 AVCCAUXRXB_112 RXPPADB_112 VTRXB_112 RXNPADB_112 AVCCAUXRXA_113 RXPPADA_113 VTRXA_113 RXNPADA_113 AVCCAUXMGT_113 AVCCAUXTX_113 VTTXA_113 TXPPADA_113 TXNPADA_113 VTTXB_113 TXPPADB_113 TXNPADB_113 AVCCAUXRXB_113 RXPPADB_113 VTRXB_113 RXNPADB_113 MGTCLK_P_113 MGTCLK_N_113 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 70 VTTXA_114 TXPPADA_114 TXNPADA_114 VTTXB_114 TXPPADB_114 TXNPADB_114 AVCCAUXRXB_114 RXPPADB_114 VTRXB_114 RXNPADB_114 GNDA_101 GNDA_101 GNDA_101 GNDA_101 GNDA_101 GNDA_101 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 GNDA_102 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 71 AP16 GNDA_106 AN19 GNDA_106 AN21 GNDA_106 AN24 GNDA_106 AN26 GNDA_109 GNDA_109 GNDA_109 AN11 GNDA_109 AN13 GNDA_109 AN16 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_112 GNDA_112 GNDA_112 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 72 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_114 GNDA_114 GNDA_114 GNDA_114 GNDA_114 GNDA_114 VREFN_SM AL17 VREFP_SM AL16 AVDD_SM AL15 VN_SM AM17 VP_SM AM16 AVSS_SM AM15 VREFN_ADC VREFP_ADC AVDD_ADC VN_ADC VP_ADC AVSS_ADC www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 73 CF1144 (FX60) Ceramic Flip-Chip Column Grid Package Table 2-2: CF1144 Package(FX60) (Cont’d) Bank Pin Description No Connects Number AK10 AC11 AF12 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 74 Chapter 2: Pinout Tables Table 2-2: CF1144 Package(FX60) (Cont’d) Bank Pin Description No Connects Number AJ13 AB14 AM14 AC15 AE15 AH16 AA17 AC17 AB18 AD18 AM18 AA19 AG19 AB20 AK20 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 75 CF1144 (FX60) Ceramic Flip-Chip Column Grid Package Table 2-2: CF1144 Package(FX60) (Cont’d) Bank Pin Description No Connects Number AA21 AC21 AF22 AA23 AJ23 AB24 AM24 AE25 AH26 AA27 AL27 AD28 AG29 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 76 VCCAUX VCCAUX VCCAUX VCCAUX AB16 VCCAUX AD16 VCCAUX VCCAUX VCCAUX VCCAUX AC19 VCCAUX VCCAUX AB22 VCCAUX VCCAUX VCCAUX VCCAUX VCCINT VCCINT VCCINT VCCINT AA10 VCCINT VCCINT VCCINT VCCINT VCCINT www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 77 AD15 VCCINT VCCINT VCCINT VCCINT AC16 VCCINT VCCINT VCCINT VCCINT VCCINT AB17 VCCINT AD17 VCCINT VCCINT VCCINT VCCINT VCCINT AA18 VCCINT AC18 VCCINT VCCINT VCCINT VCCINT AB19 VCCINT VCCINT Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 78 Virtex-4 Configuration Guide. CC_CONFIG 2. Connect this reserved pin to GND. 3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V is acceptable). CCAUX www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 79: Cf1509 (Fx140) Ceramic Flip-Chip Column Grid Package

    VBATT_0 M2_0 PWRDWN_B_0 TMS_0 AA16 M0_0 TDO_0 AB16 TCK_0 AA18 M1_0 DOUT_BUSY_0 AA20 TDI_0 AB17 TDN_0 TDP_0 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 80 IO_L11N_GC_LC_1 IO_L12P_GC_LC_1 IO_L12N_GC_VREF_LC_1 IO_L13P_GC_LC_1 IO_L13N_GC_LC_1 IO_L14P_GC_LC_1 IO_L14N_GC_LC_1 IO_L15P_GC_LC_1 IO_L15N_GC_LC_1 IO_L16P_GC_CC_LC_1 IO_L16N_GC_CC_LC_1 IO_L17P_CC_LC_1 IO_L17N_CC_LC_1 IO_L18P_VRN_LC_1 IO_L18N_VRP_LC_1 IO_L19P_LC_1 IO_L19N_LC_1 IO_L20P_LC_1 IO_L20N_VREF_LC_1 IO_L21P_LC_1 IO_L21N_LC_1 IO_L22P_LC_1 IO_L22N_LC_1 IO_L23P_LC_1 IO_L23N_LC_1 IO_L24P_LC_1 IO_L24N_LC_1 IO_L1P_D15_CC_LC_2 AM25 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 81 AH22 IO_L13N_GC_LC_2 AG21 IO_L14P_GC_LC_2 AP19 IO_L14N_GC_LC_2 AN19 IO_L15P_GC_LC_2 AG22 IO_L15N_GC_LC_2 AF21 IO_L16P_GC_LC_2 AG20 IO_L16N_GC_LC_2 AH19 IO_L17P_LC_2 AH24 IO_L17N_LC_2 AH23 IO_L18P_LC_2 AK17 IO_L18N_LC_2 AJ17 IO_L19P_LC_2 AT23 IO_L19N_LC_2 AU23 IO_L20P_LC_2 AG17 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 82 IO_L5N_GC_LC_3 IO_L6P_GC_LC_3 IO_L6N_GC_LC_3 IO_L7P_GC_LC_3 IO_L7N_GC_LC_3 IO_L8P_GC_LC_3 IO_L8N_GC_LC_3 IO_L1P_GC_LC_4 AP22 IO_L1N_GC_LC_4 AP21 IO_L2P_GC_LC_4 AN20 IO_L2N_GC_LC_4 AP20 IO_L3P_GC_LC_4 AM22 IO_L3N_GC_LC_4 AN22 IO_L4P_GC_LC_4 AL20 IO_L4N_GC_VREF_LC_4 AL19 IO_L5P_GC_LC_4 AK21 IO_L5N_GC_LC_4 AL21 IO_L6P_GC_LC_4 AK19 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 83 IO_L2N_ADC6_5 IO_L3P_ADC5_5 IO_L3N_ADC5_5 IO_L4P_5 IO_L4N_VREF_5 IO_L5P_ADC4_5 IO_L5N_ADC4_5 IO_L6P_ADC3_5 IO_L6N_ADC3_5 IO_L7P_ADC2_5 IO_L7N_ADC2_5 IO_L8P_CC_ADC1_LC_5 IO_L8N_CC_ADC1_LC_5 IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 84 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 IO_L15P_5 IO_L15N_5 IO_L16P_5 IO_L16N_5 IO_L25P_CC_LC_5 IO_L25N_CC_LC_5 IO_L26P_5 IO_L26N_5 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 85 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 IO_L17N_6 IO_L18P_6 IO_L18N_6 IO_L19P_6 IO_L19N_6 IO_L20P_6 IO_L20N_VREF_6 IO_L21P_6 IO_L21N_6 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 86 AU31 IO_L26P_SM6_7 AR29 IO_L26N_SM6_7 AT29 IO_L27P_SM5_7 AP31 IO_L27N_SM5_7 AR31 IO_L28P_7 AN29 IO_L28N_VREF_7 AP29 IO_L29P_SM4_7 AL30 IO_L29N_SM4_7 AM30 IO_L30P_SM3_7 AT30 IO_L30N_SM3_7 AU30 IO_L31P_SM2_7 AN30 IO_L31N_SM2_7 AP30 IO_L32P_SM1_7 AK29 IO_L32N_SM1_7 AL29 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 87 AT25 IO_L5P_7 AP36 IO_L5N_7 AR36 IO_L6P_7 AP25 IO_L6N_7 AP24 IO_L7P_7 AP35 IO_L7N_7 AP34 IO_L8P_CC_LC_7 AU26 IO_L8N_CC_LC_7 AT26 IO_L9P_CC_LC_7 AT35 IO_L9N_CC_LC_7 AU35 IO_L10P_7 AR26 IO_L10N_7 AP26 IO_L11P_7 AR34 IO_L11N_7 AT34 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 88 IO_L31P_8 AU13 IO_L31N_8 AU12 IO_L32P_8 AK11 IO_L32N_8 AJ11 IO_L17P_8 AN14 IO_L17N_8 AP14 IO_L18P_8 AP10 IO_L18N_8 AN10 IO_L19P_8 AK13 IO_L19N_8 AK12 IO_L20P_8 AJ10 IO_L20N_VREF_8 IO_L21P_8 AJ12 IO_L21N_8 AH12 IO_L22P_8 AM10 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 89 AR16 IO_L8P_CC_LC_8 IO_L8N_CC_LC_8 IO_L9P_CC_LC_8 AT15 IO_L9N_CC_LC_8 AU15 IO_L10P_8 IO_L10N_8 IO_L11P_8 AN15 IO_L11N_8 AP15 IO_L12P_8 IO_L12N_VREF_8 IO_L13P_8 AM15 IO_L13N_8 AL14 IO_L14P_8 IO_L14N_8 IO_L15P_8 AJ14 IO_L15N_8 AK14 IO_L16P_8 AU10 IO_L16N_8 AT10 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 90 IO_L21N_9 IO_L22P_9 IO_L22N_9 IO_L23P_VRN_9 IO_L23N_VRP_9 IO_L24P_CC_LC_9 IO_L24N_CC_LC_9 IO_L1P_9 IO_L1N_9 IO_L2P_9 IO_L2N_9 IO_L3P_9 IO_L3N_9 IO_L4P_9 IO_L4N_VREF_9 IO_L5P_9 IO_L5N_9 IO_L6P_9 IO_L6N_9 IO_L7P_9 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 91 IO_L16P_9 IO_L16N_9 IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 IO_L26P_9 IO_L26N_9 IO_L27P_9 IO_L27N_9 IO_L28P_9 IO_L28N_VREF_9 IO_L29P_9 IO_L29N_9 IO_L30P_9 IO_L30N_9 IO_L31P_9 IO_L31N_9 IO_L32P_9 IO_L32N_9 IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 92 IO_L3P_10 IO_L3N_10 IO_L4P_10 IO_L4N_VREF_10 IO_L5P_10 IO_L5N_10 IO_L6P_10 IO_L6N_10 IO_L7P_10 IO_L7N_10 IO_L8P_CC_LC_10 IO_L8N_CC_LC_10 IO_L9P_CC_LC_10 IO_L9N_CC_LC_10 IO_L10P_10 IO_L10N_10 IO_L11P_10 IO_L11N_10 IO_L12P_10 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 93 AK36 IO_L21P_11 AF30 IO_L21N_11 AG30 IO_L22P_11 AL36 IO_L22N_11 AM36 IO_L23P_VRN_11 AH33 IO_L23N_VRP_11 AJ32 IO_L24P_CC_LC_11 AK34 IO_L24N_CC_LC_11 AL34 IO_L1P_11 AC30 IO_L1N_11 AC29 IO_L2P_11 AC28 IO_L2N_11 AD27 IO_L3P_11 AD35 IO_L3N_11 AD34 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 94 AE33 IO_L16P_11 AH35 IO_L16N_11 AJ35 IO_L25P_CC_LC_11 AF29 IO_L25N_CC_LC_11 AE28 IO_L26P_11 AN35 IO_L26N_11 AN34 IO_L27P_11 AM37 IO_L27N_11 AN37 IO_L28P_11 AH30 IO_L28N_VREF_11 AH29 IO_L29P_11 AL35 IO_L29N_11 AM35 IO_L30P_11 AM33 IO_L30N_11 AN33 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 95 IO_L24N_CC_LC_12 IO_L1P_12 AB12 IO_L1N_12 AB11 IO_L2P_12 AB10 IO_L2N_12 AC10 IO_L3P_12 AA14 IO_L3N_12 AA13 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 AC12 IO_L5N_12 AD11 IO_L6P_12 AD10 IO_L6N_12 IO_L7P_12 AC13 IO_L7N_12 AB13 IO_L8P_CC_LC_12 IO_L8N_CC_LC_12 IO_L9P_CC_LC_12 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 96 IO_L16P_12 IO_L16N_12 IO_L25P_CC_LC_12 IO_L25N_CC_LC_12 IO_L26P_12 IO_L26N_12 IO_L27P_12 AH10 IO_L27N_12 IO_L28P_12 IO_L28N_VREF_12 IO_L29P_12 IO_L29N_12 IO_L30P_12 IO_L30N_12 IO_L31P_12 IO_L31N_12 IO_L32P_12 IO_L32N_12 IO_L17P_13 AA36 IO_L17N_13 AB36 IO_L18P_13 AA35 IO_L18N_13 AB35 IO_L19P_13 IO_L19N_13 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 97 AA24 IO_L1P_13 IO_L1N_13 IO_L2P_13 IO_L2N_13 IO_L3P_13 IO_L3N_13 IO_L4P_13 IO_L4N_VREF_13 IO_L5P_13 IO_L5N_13 IO_L6P_13 IO_L6N_13 IO_L7P_13 IO_L7N_13 IO_L8P_CC_LC_13 IO_L8N_CC_LC_13 IO_L9P_CC_LC_13 IO_L9N_CC_LC_13 IO_L10P_13 IO_L10N_13 IO_L11P_13 IO_L11N_13 IO_L12P_13 IO_L12N_VREF_13 IO_L13P_13 IO_L13N_13 IO_L14P_13 IO_L14N_13 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 98 IO_L29N_13 AB27 IO_L30P_13 AB26 IO_L30N_13 AB25 IO_L31P_13 AA29 IO_L31N_13 IO_L32P_13 AA28 IO_L32N_13 IO_L17P_14 IO_L17N_14 IO_L18P_14 IO_L18N_14 IO_L19P_14 IO_L19N_14 IO_L20P_14 IO_L20N_VREF_14 IO_L21P_14 IO_L21N_14 IO_L22P_14 IO_L22N_14 IO_L23P_VRN_14 IO_L23N_VRP_14 IO_L24P_CC_LC_14 IO_L24N_CC_LC_14 IO_L1P_14 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 99 IO_L6P_14 IO_L6N_14 IO_L7P_14 IO_L7N_14 IO_L8P_CC_LC_14 IO_L8N_CC_LC_14 IO_L9P_CC_LC_14 IO_L9N_CC_LC_14 IO_L10P_14 IO_L10N_14 IO_L11P_14 IO_L11N_14 IO_L12P_14 IO_L12N_VREF_14 IO_L13P_14 IO_L13N_14 IO_L14P_14 IO_L14N_14 IO_L15P_14 IO_L15N_14 IO_L16P_14 IO_L16N_14 IO_L25P_CC_LC_14 IO_L25N_CC_LC_14 IO_L26P_14 IO_L26N_14 IO_L27P_14 IO_L27N_14 IO_L28P_14 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 100 VCCO_1 VCCO_2 AF22 VCCO_2 AT22 VCCO_2 AJ23 VCCO_2 AM24 VCCO_2 AH16 VCCO_2 AL17 VCCO_2 AP18 VCCO_2 AU18 VCCO_2 AG19 VCCO_3 VCCO_3 VCCO_4 AK20 VCCO_4 AN21 VCCO_5 VCCO_5 VCCO_5 VCCO_5 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 101 VCCO_7 AN31 VCCO_7 AT32 VCCO_7 AR35 VCCO_7 AU37 VCCO_8 VCCO_8 VCCO_8 AK10 VCCO_8 AN11 VCCO_8 AT12 VCCO_8 AJ13 VCCO_8 AM14 VCCO_8 AR15 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 VCCO_9 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 102 VCCO_11 AE35 VCCO_11 AH36 VCCO_11 AL37 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 AC11 VCCO_12 AB14 VCCO_13 AB24 VCCO_13 AA27 VCCO_13 VCCO_13 VCCO_13 AB34 VCCO_13 VCCO_13 VCCO_13 AA37 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 103 VCCO_14 VCCO_14 AVCCAUXRXA_101 RXPPADA_101 VTRXA_101 RXNPADA_101 AVCCAUXMGT_101 AVCCAUXTX_101 VTTXA_101 TXPPADA_101 TXNPADA_101 VTTXB_101 TXPPADB_101 TXNPADB_101 AVCCAUXRXB_101 RXPPADB_101 VTRXB_101 RXNPADB_101 AVCCAUXRXA_102 RXPPADA_102 VTRXA_102 RXNPADA_102 AVCCAUXMGT_102 AVCCAUXTX_102 VTTXA_102 TXPPADA_102 TXNPADA_102 VTTXB_102 TXPPADB_102 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 104 AVCCAUXRXB_103 RXPPADB_103 VTRXB_103 RXNPADB_103 AVCCAUXRXA_104 AA38 RXPPADA_104 VTRXA_104 AB39 RXNPADA_104 AA39 AVCCAUXMGT_104 AH38 AVCCAUXTX_104 AE38 VTTXA_104 AC38 TXPPADA_104 AC39 TXNPADA_104 AD39 VTTXB_104 AF38 TXPPADB_104 AE39 TXNPADB_104 AF39 AVCCAUXRXB_104 AJ38 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 105 AV34 MGTVREF_105 AV32 AVCCAUXRXA_106 AV30 RXPPADA_106 AW31 VTRXA_106 AW29 RXNPADA_106 AW30 AVCCAUXMGT_106 AV22 AVCCAUXTX_106 AV25 VTTXA_106 AV28 TXPPADA_106 AW28 TXNPADA_106 AW27 VTTXB_106 AV24 TXPPADB_106 AW25 TXNPADB_106 AW24 AVCCAUXRXB_106 AV21 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 106 TXPPADB_109 AW15 TXNPADB_109 AW16 AVCCAUXRXB_109 AV19 RXPPADB_109 AW18 VTRXB_109 AW17 RXNPADB_109 AW19 AVCCAUXRXA_110 RXPPADA_110 VTRXA_110 RXNPADA_110 AVCCAUXMGT_110 AVCCAUXTX_110 VTTXA_110 TXPPADA_110 TXNPADA_110 VTTXB_110 TXPPADB_110 TXNPADB_110 AVCCAUXRXB_110 RXPPADB_110 VTRXB_110 RXNPADB_110 MGTCLK_P_110 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 107 RXNPADA_111 AVCCAUXMGT_111 AVCCAUXTX_111 VTTXA_111 TXPPADA_111 TXNPADA_111 VTTXB_111 TXPPADB_111 TXNPADB_111 AVCCAUXRXB_111 RXPPADB_111 VTRXB_111 RXNPADB_111 AVCCAUXRXA_112 RXPPADA_112 VTRXA_112 RXNPADA_112 AVCCAUXMGT_112 AVCCAUXTX_112 VTTXA_112 TXPPADA_112 TXNPADA_112 VTTXB_112 TXPPADB_112 TXNPADB_112 AVCCAUXRXB_112 RXPPADB_112 VTRXB_112 RXNPADB_112 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 108 TXPPADA_113 TXNPADA_113 VTTXB_113 TXPPADB_113 TXNPADB_113 AVCCAUXRXB_113 RXPPADB_113 VTRXB_113 RXNPADB_113 MGTCLK_P_113 MGTCLK_N_113 AVCCAUXRXA_114 RXPPADA_114 VTRXA_114 RXNPADA_114 AVCCAUXMGT_114 AVCCAUXTX_114 VTTXA_114 TXPPADA_114 TXNPADA_114 VTTXB_114 TXPPADB_114 TXNPADB_114 AVCCAUXRXB_114 RXPPADB_114 VTRXB_114 RXNPADB_114 GNDA_101 GNDA_101 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 109 GNDA_104 AK38 GNDA_104 GNDA_105 AV35 GNDA_105 AL38 GNDA_105 AN38 GNDA_105 AR38 GNDA_105 AW38 GNDA_105 AK39 GNDA_105 AV39 GNDA_105 AW20 GNDA_105 AV23 GNDA_105 AV26 GNDA_106 AW26 GNDA_106 AV27 GNDA_106 AV29 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 110 GNDA_109 AV20 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_110 GNDA_111 GNDA_111 GNDA_111 GNDA_111 GNDA_111 GNDA_111 GNDA_112 GNDA_112 GNDA_112 GNDA_112 GNDA_112 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 111 No Connects GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_113 GNDA_114 GNDA_114 GNDA_114 GNDA_114 GNDA_114 VREFN_SM AT21 VREFP_SM AT20 AVDD_SM AT19 VN_SM AU21 VP_SM AU20 AVSS_SM AU19 VREFN_ADC VREFP_ADC AVDD_ADC VN_ADC VP_ADC AVSS_ADC Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 112 Chapter 2: Pinout Tables Table 2-3: FF1517 Package Pinout (FX140) (Cont’d) Bank Pin Description Pin Number No Connects AE10 AR10 AF11 AH11 AA12 AE12 AG12 AL12 AD13 AF13 AP13 AE14 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 113 Table 2-3: FF1517 Package Pinout (FX140) (Cont’d) Bank Pin Description Pin Number No Connects AG14 AU14 AD15 AF15 AK15 AC16 AE16 AN16 AD17 AF17 AT17 AC18 AE18 AJ18 AB19 AD19 AF19 AM19 AC20 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 114 Table 2-3: FF1517 Package Pinout (FX140) (Cont’d) Bank Pin Description Pin Number No Connects AE20 AR20 AB21 AD21 AH21 AA22 AC22 AL22 AU22 AD23 AP23 AE24 AG24 AU24 AD25 AF25 AH25 AK25 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 115 Table 2-3: FF1517 Package Pinout (FX140) (Cont’d) Bank Pin Description Pin Number No Connects AC26 AE26 AG26 AJ26 AN26 AF27 AH27 AT27 AJ28 AB29 AM29 AE30 AR30 AH31 AA32 AL32 AD33 AP33 AG34 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 116 VCCAUX VCCAUX VCCAUX AM12 VCCAUX VCCAUX AL15 VCCAUX AK18 VCCAUX AA19 VCCAUX VCCAUX VCCAUX VCCAUX AL25 VCCAUX AK28 VCCAUX VCCAUX VCCAUX AB30 VCCAUX AE31 VCCAUX VCCAUX AH32 VCCAUX AC33 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 117 VCCINT VCCINT VCCINT VCCINT AD14 VCCINT AF14 VCCINT VCCINT VCCINT VCCINT AA15 VCCINT AC15 VCCINT AE15 VCCINT AG15 VCCINT AJ15 VCCINT VCCINT VCCINT AD16 VCCINT AF16 VCCINT VCCINT VCCINT Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 118 AF20 VCCINT AH20 VCCINT VCCINT VCCINT AA21 VCCINT AC21 VCCINT AE21 VCCINT VCCINT VCCINT VCCINT VCCINT AB22 VCCINT AD22 VCCINT AK22 VCCINT VCCINT VCCINT AC23 VCCINT AE23 VCCINT AG23 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 119 Virtex-4 Configuration Guide. CC_CONFIG 2. Connect this reserved pin to GND. 3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V is acceptable). CCAUX Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...

  • Page 120: Cf1509 (Lx200) Ceramic Flip-Chip Column Grid Package

    VBATT_0 M2_0 PWRDWN_B_0 TMS_0 AA16 M0_0 TDO_0 AB16 TCK_0 AA18 M1_0 DOUT_BUSY_0 AA20 TDI_0 AB17 TDN_0 TDP_0 IO_L1P_D31_LC_1 IO_L1N_D30_LC_1 IO_L2P_D29_LC_1 IO_L2N_D28_LC_1 IO_L3P_D27_LC_1 IO_L3N_D26_LC_1 IO_L4P_D25_LC_1 IO_L4N_D24_VREF_LC_1 IO_L5P_D23_LC_1 IO_L5N_D22_LC_1 IO_L6P_D21_LC_1 IO_L6N_D20_LC_1 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 121 IO_L11N_GC_LC_1 IO_L12P_GC_LC_1 IO_L12N_GC_VREF_LC_1 IO_L13P_GC_LC_1 IO_L13N_GC_LC_1 IO_L14P_GC_LC_1 IO_L14N_GC_LC_1 IO_L15P_GC_LC_1 IO_L15N_GC_LC_1 IO_L16P_GC_CC_LC_1 IO_L16N_GC_CC_LC_1 IO_L17P_CC_LC_1 IO_L17N_CC_LC_1 IO_L18P_VRN_LC_1 IO_L18N_VRP_LC_1 IO_L19P_LC_1 IO_L19N_LC_1 IO_L20P_LC_1 IO_L20N_VREF_LC_1 IO_L21P_LC_1 IO_L21N_LC_1 IO_L22P_LC_1 IO_L22N_LC_1 IO_L23P_LC_1 IO_L23N_LC_1 IO_L24P_LC_1 IO_L24N_LC_1 IO_L25P_LC_1 IO_L25N_LC_1 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 122 IO_L33N_CC_LC_1 IO_L34P_LC_1 IO_L34N_LC_1 IO_L35P_LC_1 IO_L35N_LC_1 IO_L36P_LC_1 IO_L36N_VREF_LC_1 IO_L37P_LC_1 IO_L37N_LC_1 IO_L38P_LC_1 IO_L38N_LC_1 IO_L39P_LC_1 IO_L39N_LC_1 IO_L40P_LC_1 IO_L40N_LC_1 IO_L1P_D15_CC_LC_2 AN25 IO_L1N_D14_CC_LC_2 AN24 IO_L2P_D13_LC_2 AT14 IO_L2N_D12_LC_2 AR14 IO_L3P_D11_LC_2 AV24 IO_L3N_D10_LC_2 AW24 IO_L4P_D9_LC_2 AV15 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 123 AU20 IO_L16N_GC_LC_2 AT20 IO_L17P_LC_2 AG22 IO_L17N_LC_2 AF21 IO_L18P_LC_2 AH17 IO_L18N_LC_2 AG17 IO_L19P_LC_2 AE22 IO_L19N_LC_2 AD21 IO_L20P_LC_2 AE18 IO_L20N_VREF_LC_2 AD17 IO_L21P_LC_2 AV22 IO_L21N_LC_2 AW22 IO_L22P_LC_2 AU18 IO_L22N_LC_2 AT18 IO_L23P_VRN_LC_2 AU22 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 124 AW16 IO_L34N_LC_2 AW15 IO_L35P_LC_2 AC22 IO_L35N_LC_2 AC20 IO_L36P_LC_2 AT16 IO_L36N_VREF_LC_2 AT15 IO_L37P_LC_2 AU23 IO_L37N_LC_2 AV23 IO_L38P_LC_2 AR16 IO_L38N_LC_2 AP16 IO_L39P_LC_2 AR23 IO_L39N_LC_2 AT23 IO_L40P_CC_LC_2 AK16 IO_L40N_CC_LC_2 AJ16 IO_L1P_GC_CC_LC_3 IO_L1N_GC_CC_LC_3 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 125 AJ21 IO_L3N_GC_LC_4 AJ20 IO_L4P_GC_LC_4 AG20 IO_L4N_GC_VREF_LC_4 AF20 IO_L5P_GC_LC_4 AL20 IO_L5N_GC_LC_4 AL19 IO_L6P_GC_LC_4 AH18 IO_L6N_GC_LC_4 AG18 IO_L7P_GC_VRN_LC_4 AL21 IO_L7N_GC_VRP_LC_4 AK21 IO_L8P_GC_CC_LC_4 AK19 IO_L8N_GC_CC_LC_4 AJ19 IO_L1P_ADC7_5 IO_L1N_ADC7_5 IO_L2P_ADC6_5 IO_L2N_ADC6_5 IO_L3P_ADC5_5 IO_L3N_ADC5_5 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 126 IO_L8N_CC_ADC1_LC_5 IO_L17P_5 IO_L17N_5 IO_L18P_5 IO_L18N_5 IO_L19P_5 IO_L19N_5 IO_L20P_5 IO_L20N_VREF_5 IO_L21P_5 IO_L21N_5 IO_L22P_5 IO_L22N_5 IO_L23P_VRN_5 IO_L23N_VRP_5 IO_L24P_CC_LC_5 IO_L24N_CC_LC_5 IO_L9P_CC_LC_5 IO_L9N_CC_LC_5 IO_L10P_5 IO_L10N_5 IO_L11P_5 IO_L11N_5 IO_L12P_5 IO_L12N_VREF_5 IO_L13P_5 IO_L13N_5 IO_L14P_5 IO_L14N_5 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 127 IO_L27P_5 IO_L27N_5 IO_L28P_5 IO_L28N_VREF_5 IO_L29P_5 IO_L29N_5 IO_L30P_5 IO_L30N_5 IO_L31P_5 IO_L31N_5 IO_L32P_5 IO_L32N_5 IO_L1P_6 IO_L1N_6 IO_L2P_6 IO_L2N_6 IO_L3P_6 IO_L3N_6 IO_L4P_6 IO_L4N_VREF_6 IO_L5P_6 IO_L5N_6 IO_L6P_6 IO_L6N_6 IO_L7P_6 IO_L7N_6 IO_L8P_CC_LC_6 IO_L8N_CC_LC_6 IO_L17P_6 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 128 IO_L22P_6 IO_L22N_6 IO_L23P_VRN_6 IO_L23N_VRP_6 IO_L24P_CC_LC_6 IO_L24N_CC_LC_6 IO_L9P_CC_LC_6 IO_L9N_CC_LC_6 IO_L10P_6 IO_L10N_6 IO_L11P_6 IO_L11N_6 IO_L12P_6 IO_L12N_VREF_6 IO_L13P_6 IO_L13N_6 IO_L14P_6 IO_L14N_6 IO_L15P_6 IO_L15N_6 IO_L16P_6 IO_L16N_6 IO_L25P_CC_LC_6 IO_L25N_CC_LC_6 IO_L26P_6 IO_L26N_6 IO_L27P_6 IO_L27N_6 IO_L28P_6 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 129 AU27 IO_L32P_SM1_7 AT28 IO_L32N_SM1_7 AR28 IO_L17P_7 AL26 IO_L17N_7 AM27 IO_L18P_7 AU31 IO_L18N_7 AU32 IO_L19P_7 AV28 IO_L19N_7 AU28 IO_L20P_7 AW32 IO_L20N_VREF_7 AV32 IO_L21P_7 AW25 IO_L21N_7 AW26 IO_L22P_7 AP29 IO_L22N_7 AN29 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 130 AW34 IO_L10N_7 AV34 IO_L11P_7 AW30 IO_L11N_7 AW31 IO_L12P_7 AV33 IO_L12N_VREF_7 AU33 IO_L13P_7 AP25 IO_L13N_7 AP26 IO_L14P_7 AT31 IO_L14N_7 AT30 IO_L15P_7 AU25 IO_L15N_7 AV25 IO_L16P_7 AR31 IO_L16N_7 AR32 IO_L25P_CC_LC_8 AW12 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 131 IO_L18P_8 IO_L18N_8 IO_L19P_8 AR12 IO_L19N_8 AP12 IO_L20P_8 IO_L20N_VREF_8 IO_L21P_8 AV13 IO_L21N_8 AU13 IO_L22P_8 AT10 IO_L22N_8 IO_L23P_VRN_8 AU12 IO_L23N_VRP_8 AU11 IO_L24P_CC_LC_8 IO_L24N_CC_LC_8 IO_L1P_8 IO_L1N_8 IO_L2P_8 AJ10 IO_L2N_8 IO_L3P_8 IO_L3N_8 IO_L4P_8 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 132 AM10 IO_L12N_VREF_8 AL10 IO_L13P_8 AM11 IO_L13N_8 AN10 IO_L14P_8 AH13 IO_L14N_8 AJ12 IO_L15P_8 AN12 IO_L15N_8 AP11 IO_L16P_8 IO_L16N_8 IO_L17P_9 IO_L17N_9 IO_L18P_9 IO_L18N_9 IO_L19P_9 IO_L19N_9 IO_L20P_9 IO_L20N_VREF_9 IO_L21P_9 IO_L21N_9 IO_L22P_9 IO_L22N_9 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 133 IO_L3N_9 IO_L4P_9 IO_L4N_VREF_9 IO_L5P_9 IO_L5N_9 IO_L6P_9 IO_L6N_9 IO_L7P_9 IO_L7N_9 IO_L8P_CC_LC_9 IO_L8N_CC_LC_9 IO_L9P_CC_LC_9 IO_L9N_CC_LC_9 IO_L10P_9 IO_L10N_9 IO_L11P_9 IO_L11N_9 IO_L12P_9 IO_L12N_VREF_9 IO_L13P_9 IO_L13N_9 IO_L14P_9 IO_L14N_9 IO_L15P_9 IO_L15N_9 IO_L16P_9 IO_L16N_9 IO_L25P_CC_LC_9 IO_L25N_CC_LC_9 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 134 IO_L30P_9 IO_L30N_9 IO_L31P_9 IO_L31N_9 IO_L32P_9 IO_L32N_9 IO_L17P_10 IO_L17N_10 IO_L18P_10 IO_L18N_10 IO_L19P_10 IO_L19N_10 IO_L20P_10 IO_L20N_VREF_10 IO_L21P_10 IO_L21N_10 IO_L22P_10 IO_L22N_10 IO_L23P_VRN_10 IO_L23N_VRP_10 IO_L24P_CC_LC_10 IO_L24N_CC_LC_10 IO_L1P_10 IO_L1N_10 IO_L2P_10 IO_L2N_10 IO_L3P_10 IO_L3N_10 IO_L4P_10 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 135 IO_L9P_CC_LC_10 IO_L9N_CC_LC_10 IO_L10P_10 IO_L10N_10 IO_L11P_10 IO_L11N_10 IO_L12P_10 IO_L12N_VREF_10 IO_L13P_10 IO_L13N_10 IO_L14P_10 IO_L14N_10 IO_L15P_10 IO_L15N_10 IO_L16P_10 IO_L16N_10 IO_L25P_CC_LC_10 IO_L25N_CC_LC_10 IO_L26P_10 IO_L26N_10 IO_L27P_10 IO_L27N_10 IO_L28P_10 IO_L28N_VREF_10 IO_L29P_10 IO_L29N_10 IO_L30P_10 IO_L30N_10 IO_L31P_10 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 136 AD29 IO_L3P_11 AD27 IO_L3N_11 AC27 IO_L4P_11 AE31 IO_L4N_VREF_11 AE32 IO_L5P_11 AD26 IO_L5N_11 AE26 IO_L6P_11 AF31 IO_L6N_11 AG32 IO_L7P_11 AH32 IO_L7N_11 AH33 IO_L8P_CC_LC_11 AJ34 IO_L8N_CC_LC_11 AH34 IO_L9P_CC_LC_11 AD25 IO_L9N_CC_LC_11 AE24 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 137 AT35 IO_L28P_11 AT36 IO_L28N_VREF_11 AR36 IO_L29P_11 AW36 IO_L29N_11 AW37 IO_L30P_11 AV37 IO_L30N_11 AU37 IO_L31P_11 AW35 IO_L31N_11 AV35 IO_L32P_11 AR34 IO_L32N_11 AP34 IO_L17P_12 IO_L17N_12 IO_L18P_12 IO_L18N_12 IO_L19P_12 AH10 IO_L19N_12 IO_L20P_12 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 138 IO_L3P_12 IO_L3N_12 IO_L4P_12 IO_L4N_VREF_12 IO_L5P_12 IO_L5N_12 IO_L6P_12 IO_L6N_12 IO_L7P_12 IO_L7N_12 IO_L8P_CC_LC_12 IO_L8N_CC_LC_12 IO_L9P_CC_LC_12 IO_L9N_CC_LC_12 IO_L10P_12 IO_L10N_12 IO_L11P_12 AF11 IO_L11N_12 AG10 IO_L12P_12 AE12 IO_L12N_VREF_12 AE11 IO_L13P_12 IO_L13N_12 IO_L14P_12 IO_L14N_12 IO_L15P_12 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 139 IO_L27N_12 IO_L28P_12 IO_L28N_VREF_12 IO_L29P_12 IO_L29N_12 IO_L30P_12 IO_L30N_12 IO_L31P_12 IO_L31N_12 IO_L32P_12 IO_L32N_12 IO_L17P_13 IO_L17N_13 IO_L18P_13 IO_L18N_13 IO_L19P_13 IO_L19N_13 IO_L20P_13 IO_L20N_VREF_13 IO_L21P_13 IO_L21N_13 IO_L22P_13 IO_L22N_13 IO_L23P_VRN_13 IO_L23N_VRP_13 IO_L24P_CC_LC_13 IO_L24N_CC_LC_13 IO_L1P_13 IO_L1N_13 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 140 IO_L7P_13 IO_L7N_13 IO_L8P_CC_LC_13 IO_L8N_CC_LC_13 IO_L9P_CC_LC_13 IO_L9N_CC_LC_13 IO_L10P_13 IO_L10N_13 IO_L11P_13 IO_L11N_13 IO_L12P_13 IO_L12N_VREF_13 IO_L13P_13 IO_L13N_13 IO_L14P_13 IO_L14N_13 IO_L15P_13 IO_L15N_13 IO_L16P_13 IO_L16N_13 IO_L25P_CC_LC_13 IO_L25N_CC_LC_13 IO_L26P_13 IO_L26N_13 IO_L27P_13 IO_L27N_13 IO_L28P_13 IO_L28N_VREF_13 AA39 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 141 IO_L17P_14 IO_L17N_14 IO_L18P_14 IO_L18N_14 IO_L19P_14 IO_L19N_14 IO_L20P_14 IO_L20N_VREF_14 IO_L21P_14 IO_L21N_14 IO_L22P_14 IO_L22N_14 IO_L23P_VRN_14 IO_L23N_VRP_14 IO_L24P_CC_LC_14 IO_L24N_CC_LC_14 IO_L1P_14 IO_L1N_14 IO_L2P_14 IO_L2N_14 IO_L3P_14 IO_L3N_14 IO_L4P_14 IO_L4N_VREF_14 IO_L5P_14 IO_L5N_14 IO_L6P_14 IO_L6N_14 IO_L7P_14 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 142 IO_L13N_14 IO_L14P_14 IO_L14N_14 IO_L15P_14 IO_L15N_14 IO_L16P_14 IO_L16N_14 IO_L25P_CC_LC_14 IO_L25N_CC_LC_14 IO_L26P_14 IO_L26N_14 IO_L27P_14 IO_L27N_14 IO_L28P_14 IO_L28N_VREF_14 IO_L29P_14 IO_L29N_14 IO_L30P_14 AA10 IO_L30N_14 IO_L31P_14 AA11 IO_L31N_14 IO_L32P_14 IO_L32N_14 IO_L17P_15 AB27 IO_L17N_15 AB28 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 143 IO_L5N_15 AC39 IO_L6P_15 AA31 IO_L6N_15 IO_L7P_15 AC35 IO_L7N_15 AB35 IO_L8P_CC_LC_15 AB33 IO_L8N_CC_LC_15 AA33 IO_L9P_CC_LC_15 AC33 IO_L9N_CC_LC_15 AC34 IO_L10P_15 AD37 IO_L10N_15 AC37 IO_L11P_15 AC32 IO_L11N_15 AB31 IO_L12P_15 AE39 IO_L12N_VREF_15 AD39 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 144 AL38 IO_L30N_15 AL39 IO_L31P_15 AM36 IO_L31N_15 AL36 IO_L32P_15 AK36 IO_L32N_15 AK37 IO_L17P_16 IO_L17N_16 IO_L18P_16 IO_L18N_16 IO_L19P_16 IO_L19N_16 IO_L20P_16 AB13 IO_L20N_VREF_16 AC13 IO_L21P_16 AB15 IO_L21N_16 AC14 IO_L22P_16 AC10 IO_L22N_16 IO_L23P_VRN_16 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 145 IO_L7P_16 IO_L7N_16 IO_L8P_CC_LC_16 IO_L8N_CC_LC_16 IO_L9P_CC_LC_16 AA14 IO_L9N_CC_LC_16 AA13 IO_L10P_16 IO_L10N_16 IO_L11P_16 IO_L11N_16 IO_L12P_16 IO_L12N_VREF_16 IO_L13P_16 IO_L13N_16 IO_L14P_16 IO_L14N_16 IO_L15P_16 AB11 IO_L15N_16 AB10 IO_L16P_16 IO_L16N_16 IO_L25P_CC_LC_16 AC12 IO_L25N_CC_LC_16 AD11 IO_L26P_16 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 146 VCCO_0 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_1 VCCO_2 AC21 VCCO_2 AD18 VCCO_2 AF22 VCCO_2 AH16 VCCO_2 AJ23 VCCO_2 AL17 VCCO_2 AM24 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 147 VCCO_5 VCCO_5 VCCO_5 VCCO_5 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_6 VCCO_7 AK30 VCCO_7 AL27 VCCO_7 AN31 VCCO_7 AP28 VCCO_7 AR25 VCCO_7 AT32 VCCO_7 AU29 VCCO_7 AV26 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 148 VCCO_9 VCCO_9 VCCO_9 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_10 VCCO_11 AD28 VCCO_11 AE25 VCCO_11 AF32 VCCO_11 AG29 VCCO_11 AJ33 VCCO_11 AM34 VCCO_11 AP38 VCCO_11 AR35 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 149 VCCO_13 VCCO_13 VCCO_13 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_14 VCCO_15 AA27 VCCO_15 AB34 VCCO_15 AC31 VCCO_15 AD38 VCCO_15 AE35 VCCO_15 AG39 VCCO_15 AH36 VCCO_15 AL37 VCCO_15 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 150 VCCO_16 VCCO_16 AB14 VCCO_16 VCCO_16 VCCO_16 AC11 VCCO_16 VCCO_16 VCCO_16 VCCO_16 VREFN_SM AV19 VREFP_SM AV20 AVDD_SM AW21 VN_SM AW19 VP_SM AW20 AVSS_SM AV18 VREFN_ADC VREFP_ADC AVDD_ADC VN_ADC VP_ADC AVSS_ADC www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 151 CF1509 (LX200) Ceramic Flip-Chip Column Grid Package Table 2-4: CF1509 Package Pinout (LX200) (Cont’d) Bank Pin Description Pin Number No Connect AE10 AR10 AH11 AV11 AA12 AG12 AL12 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 152 Table 2-4: CF1509 Package Pinout (LX200) (Cont’d) Bank Pin Description Pin Number No Connect AD13 AF13 AK13 AP13 AE14 AG14 AJ14 AU14 AD15 AF15 AK15 AC16 AE16 AN16 AF17 AT17 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 153 Table 2-4: CF1509 Package Pinout (LX200) (Cont’d) Bank Pin Description Pin Number No Connect AC18 AJ18 AW18 AB19 AD19 AM19 AE20 AR20 AB21 AH21 AV21 AA22 AL22 AB23 AD23 AP23 AA24 AC24 AG24 AU24 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 154 Table 2-4: CF1509 Package Pinout (LX200) (Cont’d) Bank Pin Description Pin Number No Connect AB25 AF25 AH25 AK25 AA26 AC26 AG26 AJ26 AN26 AF27 AH27 AK27 AT27 AJ28 AW28 AB29 AM29 AE30 AR30 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 155 Table 2-4: CF1509 Package Pinout (LX200) (Cont’d) Bank Pin Description Pin Number No Connect AH31 AV31 AA32 AL32 AD33 AP33 AG34 AU34 AK35 AC36 AN36 AF37 AT37 AV38 AJ38 AW38 AB39 AM39 AV39 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 156 VCCAUX AN19 VCCAUX VCCAUX VCCAUX VCCAUX AM22 VCCAUX VCCAUX AL25 VCCAUX VCCAUX VCCAUX AK28 VCCAUX VCCAUX AC29 VCCAUX VCCAUX AF30 VCCAUX VCCAUX AJ31 VCCAUX VCCAUX AM32 VCCINT VCCINT VCCINT www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 157 VCCINT VCCINT VCCINT VCCINT AE13 VCCINT AG13 VCCINT AN13 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT AD14 VCCINT AF14 VCCINT AH14 VCCINT AK14 VCCINT VCCINT VCCINT VCCINT VCCINT AA15 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 158 VCCINT VCCINT AB18 VCCINT VCCINT VCCINT VCCINT AC19 VCCINT AE19 VCCINT VCCINT VCCINT AB20 VCCINT AD20 VCCINT AP20 VCCINT VCCINT VCCINT AA21 VCCINT AE21 VCCINT AG21 VCCINT VCCINT AB22 www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...
  • Page 159 VCCINT VCCINT VCCINT VCCINT AA25 VCCINT AC25 VCCINT AG25 VCCINT AJ25 VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT AB26 VCCINT AF26 VCCINT AH26 VCCINT AK26 VCCINT AM26 VCCINT VCCINT VCCINT Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 160 Virtex-4 Configuration CC_CONFIG Guide. 2. Connect this reserved pin to GND. 3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as is acceptable). CCAUX www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 161: Chapter 3: Pinout Diagrams

    “CF1509 Color-Coded SelectIO Interface and Bank Information,” page 167 • FF1517 Package: ♦ “CF1509 Package Pinout Diagram (FX140),” page 168 ♦ “CF1509 Color-Coded SelectIO Interface and Bank Information,” page 169 Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...

  • Page 162: Cf1140 Package Pinout Diagram (Sx55)

    Notes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use. 2. Dedicated SM and ADC pins are reserved for future use. UG496_C03_01_040208 Figure 3-1: CF1140 Ceramic Flip-Chip Column Grid Pinout Diagram (SX55) www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 163: Cf1140 Color-Coded Selectio Interface And Bank Information

    8 8 8 8 8 8 8 8 2 7 7 7 7 7 7 7 7 7 7 UG496_C03_02_040208 Figure 3-2: CF1140 Color-Coded SelectIO™ Interface and Bank Information Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...

  • Page 164: Cf1144 Package Pinout Diagram (Fx60)

    Notes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use. 2. Dedicated SM and ADC pins are reserved for future use. UG496_C03_03_040208 Figure 3-3: CF1144 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX60) www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 165: Cf1144 Color-Coded Selectio Interface And Bank Information

    12 12 8 8 8 8 8 8 7 7 7 7 7 7 7 7 7 7 7 UG496_C03_04_040208 Figure 3-4: CF1144 Color-Coded SelectIO Interface and Bank Information Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...

  • Page 166: Cf1509 Package Pinout Diagram (Lx200)

    Notes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use. 2. Dedicated SM and ADC pins are reserved for future use. UG496_C03_05_040208 Figure 3-5: CF1509 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram (LX200) www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 167: Cf1509 Color-Coded Selectio Interface And Bank Information

    8 8 8 8 8 2 2 2 2 7 7 7 7 7 7 7 7 11 11 11 UG496_C03_06_040208 Figure 3-6: CF1509 Color-Coded SelectIO Interface and Bank Information Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...

  • Page 168: Cf1509 Package Pinout Diagram (Fx140)

    Notes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use. 2. Dedicated SM and ADC pins are reserved for future use. UG496_C03_07_040208 Figure 3-7: CF1509 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram (FX140) www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 169: Cf1509 Color-Coded Selectio Interface And Bank Information

    12 12 8 8 8 8 8 8 8 8 8 7 7 7 7 7 7 7 7 UG496_C03_08_040208 Figure 3-8: CF1509 Color-Coded SelectIO Interface and Bank Information Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...
  • Page 170 Chapter 3: Pinout Diagrams www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 171: Chapter 4: Mechanical Drawings

    This chapter provides mechanical drawings of the following Virtex-4 QV packages: • “CF1140 Ceramic Flip-Chip Column Grid Package Specifications” • “CF1144 Ceramic Flip-Chip Column Grid Package Specifications” • “CF1509 Ceramic Flip-Chip Column Grid Package Specifications” Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...

  • Page 172: Cf1140 Ceramic Flip-Chip Column Grid Package Specifications

    Chapter 4: Mechanical Drawings CF1140 Ceramic Flip-Chip Column Grid Package Specifications X-Ref Target - Figure 4-1 Figure 4-1: CF1140 Ceramic Flip-Chip Column Grid Package Mechanical Drawing www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 173: Cf1144 Ceramic Flip-Chip Column Grid Package Specifications

    CF1144 Ceramic Flip-Chip Column Grid Package Specifications CF1144 Ceramic Flip-Chip Column Grid Package Specifications X-Ref Target - Figure 4-2 Figure 4-2: CF1144 Ceramic Flip-Chip Column Grid Package Mechanical Drawing Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...

  • Page 174: Cf1509 Ceramic Flip-Chip Column Grid Package Specifications

    Chapter 4: Mechanical Drawings CF1509 Ceramic Flip-Chip Column Grid Package Specifications X-Ref Target - Figure 4-3 Figure 4-3: CF1509 Ceramic Flip-Chip Column Grid Package Mechanical Drawing www.xilinx.com Virtex-4 QV FPGA Ceramic Packaging UG496 (v1.1) June 8, 2012...

  • Page 175: Chapter 5: Thermal Specifications

    CTE matches well with the silicon die • Low corrosion sensitivity • Meets JEDEC MSL-1 • Meets NASA outgas requirements • 90Pb/10Sn solid copper core columns • 90Pb/10Sn die solder bumps • Silicon carbide heat-spreader Virtex-4 QV FPGA Ceramic Packaging www.xilinx.com UG496 (v1.1) June 8, 2012...

  • Page 176: Thermal Resistance And Package Mass

    Column Grid Assembly and Rework User Guide by IBM (http://www.ibm.com). Thermal Resistance and Package Mass Virtex-4 QV FPGAs are offered exclusively in CF packages for high thermal cycle reliability. The Virtex-4 QV FPGA ceramic packages thermal resistance and package mass data is listed in Table 5-1.

  • Page 177: Chapter 6: Guidelines For Xilinx Cf Package Handling And Assembly

    Guidelines for Xilinx CF Package Handling and Assembly Xilinx ceramic flip-chip (CF) packages are robust and reliable. The CF package uses high lead columns (instead of solder balls) to create a higher standoff and more flexible interconnection, which achieves a significant increase in reliability. A silicon carbide (SiC) lid covers the die and ceramic chip capacitors are placed around the periphery of the package.
  • Page 178 Chapter 6: Guidelines for Xilinx CF Package Handling and Assembly After the dry pack bag is opened and the foam-covered banded tray is removed from the bag, carefully hold positive downward pressure on top of the foam tray while cutting the heat-sealed black plastic bands (see Figure 6-2).

  • Page 179: Product Handling And Inspection

    Product Handling and Inspection All Xilinx CF package die are flip-chip and bumped with high lead bumping (95% Pb/5% Sn). The CF package substrate is ceramic. The bumped die is flipped and reflowed to the ceramic substrate at assembly. A moisture resistant epoxy underfill encapsulates the bumps.

  • Page 180: Board Level Mounting

    The design and process requirements should be compatible with standard SMT equipment and with total assembly requirements as driven by other components on the product. Xilinx recommends PCB design rules for each of our packages. These rules are specified in UG112, Device Package User Guide.

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