Xilinx VCU1287 User Manual page 75

Characterization board
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set_property PACKAGE_PIN AW41
set_property PACKAGE_PIN AV43
set_property PACKAGE_PIN AV44
set_property PACKAGE_PIN BB42
set_property PACKAGE_PIN BB43
set_property PACKAGE_PIN AW45
set_property PACKAGE_PIN AW46
set_property PACKAGE_PIN BD42
set_property PACKAGE_PIN BD43
set_property PACKAGE_PIN BA45
set_property PACKAGE_PIN BA46
set_property PACKAGE_PIN BC45
set_property PACKAGE_PIN BC46
set_property PACKAGE_PIN BF42
set_property PACKAGE_PIN BF43
set_property PACKAGE_PIN AU36
set_property PACKAGE_PIN AU37
set_property PACKAGE_PIN AV38
set_property PACKAGE_PIN AV39
set_property PACKAGE_PIN AP38
set_property PACKAGE_PIN AP39
set_property PACKAGE_PIN AP43
set_property PACKAGE_PIN AP44
set_property PACKAGE_PIN AR40
set_property PACKAGE_PIN AR41
set_property PACKAGE_PIN AR45
set_property PACKAGE_PIN AR46
set_property PACKAGE_PIN AT38
set_property PACKAGE_PIN AT39
set_property PACKAGE_PIN AT43
set_property PACKAGE_PIN AT44
set_property PACKAGE_PIN AU40
set_property PACKAGE_PIN AU41
set_property PACKAGE_PIN AU45
set_property PACKAGE_PIN AU46
set_property PACKAGE_PIN AN36
set_property PACKAGE_PIN AN37
set_property PACKAGE_PIN AR36
set_property PACKAGE_PIN AR37
set_property PACKAGE_PIN AK38
set_property PACKAGE_PIN AK39
set_property PACKAGE_PIN AK43
set_property PACKAGE_PIN AK44
set_property PACKAGE_PIN AL40
set_property PACKAGE_PIN AL41
set_property PACKAGE_PIN AL45
set_property PACKAGE_PIN AL46
set_property PACKAGE_PIN AM38
set_property PACKAGE_PIN AM39
set_property PACKAGE_PIN AM43
set_property PACKAGE_PIN AM44
set_property PACKAGE_PIN AN40
set_property PACKAGE_PIN AN41
set_property PACKAGE_PIN AN45
set_property PACKAGE_PIN AN46
set_property PACKAGE_PIN AJ36
set_property PACKAGE_PIN AJ37
set_property PACKAGE_PIN AL36
set_property PACKAGE_PIN AL37
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Appendix Appendix C:
[get_ports "124_TX3_N"]
[get_ports "124_RX3_P"]
[get_ports "124_RX3_N"]
[get_ports "124_TX2_P"]
[get_ports "124_TX2_N"]
[get_ports "124_RX2_P"]
[get_ports "124_RX2_N"]
[get_ports "124_TX1_P"]
[get_ports "124_TX1_N"]
[get_ports "124_RX1_P"]
[get_ports "124_RX1_N"]
[get_ports "124_RX0_P"]
[get_ports "124_RX0_N"]
[get_ports "124_TX0_P"]
[get_ports "124_TX0_N"]
[get_ports "125_REFCLK1_P"]
[get_ports "125_REFCLK1_N"]
[get_ports "125_REFCLK0_P"]
[get_ports "125_REFCLK0_N"]
[get_ports "125_TX3_P"]
[get_ports "125_TX3_N"]
[get_ports "125_RX3_P"]
[get_ports "125_RX3_N"]
[get_ports "125_TX2_P"]
[get_ports "125_TX2_N"]
[get_ports "125_RX2_P"]
[get_ports "125_RX2_N"]
[get_ports "125_TX1_P"]
[get_ports "125_TX1_N"]
[get_ports "125_RX1_P"]
[get_ports "125_RX1_N"]
[get_ports "125_TX0_P"]
[get_ports "125_TX0_N"]
[get_ports "125_RX0_P"]
[get_ports "125_RX0_N"]
[get_ports "126_REFCLK1_P"]
[get_ports "126_REFCLK1_N"]
[get_ports "126_REFCLK0_P"]
[get_ports "126_REFCLK0_N"]
[get_ports "126_TX3_P"]
[get_ports "126_TX3_N"]
[get_ports "126_RX3_P"]
[get_ports "126_RX3_N"]
[get_ports "126_TX2_P"]
[get_ports "126_TX2_N"]
[get_ports "126_RX2_P"]
[get_ports "126_RX2_N"]
[get_ports "126_TX1_P"]
[get_ports "126_TX1_N"]
[get_ports "126_RX1_P"]
[get_ports "126_RX1_N"]
[get_ports "126_TX0_P"]
[get_ports "126_TX0_N"]
[get_ports "126_RX0_P"]
[get_ports "126_RX0_N"]
[get_ports "127_REFCLK1_P"]
[get_ports "127_REFCLK1_N"]
[get_ports "127_REFCLK0_P"]
[get_ports "127_REFCLK0_N"]
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