Table of Contents
Advertisement
Information for each GTH transceiver clock input is shown in
Table 3-17: GTH Transceiver Reference Clock Inputs
U1 FPGA Pin
AW8
AW9
AV10
AV11
AT10
AT11
AP10
AP11
AM10
AM11
AK10
AK11
AH10
AH11
AF10
AF11
AD10
AD11
AB10
AB11
Y11
Y10
V10
V11
T10
T11
P10
P11
M10
M11
K10
K11
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Net Name
224_REFCLK0_N
224_REFCLK0_P
224_REFCLK1_N
224_REFCLK1_P
225_REFCLK0_N
225_REFCLK0_P
225_REFCLK1_N
225_REFCLK1_P
226_REFCLK0_N
226_REFCLK0_P
226_REFCLK1_N
226_REFCLK1_P
227_REFCLK0_N
227_REFCLK0_P
227_REFCLK1_N
227_REFCLK1_P
228_REFCLK0_N
228_REFCLK0_P
228_REFCLK1_N
228_REFCLK1_P
229_REFCLK0_P
229_REFCLK0_N
229_REFCLK1_N
229_REFCLK1_P
230_REFCLK0_N
230_REFCLK0_P
230_REFCLK1_N
230_REFCLK1_P
231_REFCLK0_N
231_REFCLK0_P
231_REFCLK1_N
231_REFCLK1_P
www.xilinx.com
Chapter 3:
Board Component Descriptions
Table
3-17.
Quad
224
224
224
224
225
225
225
225
226
226
226
226
227
227
227
227
228
228
228
228
229
229
229
229
230
230
230
230
231
231
231
231
Send Feedback
Connector
J40
J40
J40
J40
J88
J88
J88
J88
J89
J89
J89
J89
J41
J41
J41
J41
J42
J42
J42
J42
J92
J92
J92
J92
J43
J43
J43
J43
J156
J156
J156
J156
41
Advertisement
Table of Contents
