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Xilinx VIODC User Manual

Xilinx VIODC User Manual

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Video
Input/Output
Daughter Card
User Guide
UG235 (v1.2.1) October 31, 2007
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www.BDTIC.com/XILINX

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Summary of Contents for Xilinx VIODC

  • Page 1 Video Input/Output Daughter Card User Guide UG235 (v1.2.1) October 31, 2007 www.BDTIC.com/XILINX...
  • Page 2 Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Table Of Contents

    ........... . . 16 Chapter 2: VIODC to ML402 Card Interface VIOBUS Clocking .
  • Page 4 DVI Connectivity on VIODC ........
  • Page 5 ..............67 www.BDTIC.com/XILINX UG235 (v1.2.1) October 31, 2007...
  • Page 6 Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...
  • Page 7 Figure 1-1: VIODC Attached to an ML402 Platform ....... 15...
  • Page 8 Figure 8-2: Configuration Jumper Locations on the VIODC Top, Configured for VIODC Mounted to an ML402 Board ......54...
  • Page 9 Table A-4: VIOBUS VIODC FPGA Connections ........
  • Page 10 Appendix B: VSK I/O Connector Location Pictures www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...

  • Page 11: Preface: About This Guide

    Preface About This Guide This guide describes the Video Input and Output Daughter Card (VIODC), a standard video interface card that is compatible with the Xilinx ML401, ML402, and ML403 development platforms. Guide Contents This manual contains the following chapters: •...

  • Page 12: Conventions

    IOB #2: Name = CLKIN’ Repetitive material that has been omitted Repetitive material that has block_name allow block Horizontal ellipsis . . . been omitted loc1 loc2 ... locn; www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...

  • Page 13: Online Document

    Cross-reference link to a Red text Figure 2-5 in the Handbook. location in another document Go to http://www.xilinx.com Blue, underlined text Hyperlink to a website (URL) for the latest speed files. www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...
  • Page 14 Preface: About This Guide www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...

  • Page 15: Chapter 1: Viodc Overview

    VIODC Overview Introduction The Video Input and Output Daughter Card (VIODC) is a standard video interface card for Xilinx development platforms. It is compatible with ML401, ML402, and ML403 boards and other future Xilinx development platforms. The VIODC is shown in Figure 1-1 mounted on a ML402 platform.

  • Page 16: Video Interface Support

    DVI input. • VGA Interface – VGA input and outputs are is available on the VIODC card. The VGA output is routed to the analog output pins of the DVI output connector. It is sourced by an ADV7123 10-bit DAC. VGA input is captured by the AD9887 IC.
  • Page 17 VIODC over the XGI connector. • VIOBUS – The Video Starter Kit (VSK) uses the VIODC as a Video I/O interface. For compatibility with the VSK, the 64 XGI signals have been specified as a bus named the VIOBUS. In this use, the signals on the VIODC XGI connector have been specified as a...
  • Page 18 Chapter 1: VIODC Overview www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...

  • Page 19: Chapter 2: Viodc To Ml402 Card Interface

    When the VIODC is used as part of the Video Starter Kit (VSK) from Xilinx, the 64-pin XGI connector connects the VIODC to a ML402 card to communicate with the VIODC card. When the VIODC is used with the VSK, the 64 XGI signals are allocated to a bus named the VIOBUS, which serves the following functions: •...

  • Page 20: Viobus Signal Definitions

    Pixel enable for LVCMOS25 100 MHz VIODC hdr1[44] vio_up[25:0] Sport Serial Bus (used to configure registers in the VIODC FPGA) vio_sport_up Sport write data (16-bit LVCMOS25 10 MHz ML402 hdr1[54] data, 16-bit address) vio_sport_dn Sport return data...

  • Page 21: Chapter 3: Component And S-Video Interfaces

    Chapter 3 Component and S-Video Interfaces Overview The VIODC board supports input and output for S-video, composite, and component video. Figure 3-1 is a simplified block diagram of input and output. Control Control S-Video S-Video ADA4412 Video Video Composite Composite...

  • Page 22: Adv7321 Video Encoder

    Y (intensity) and C (color) signals are each conditioned and input into the ADV7403 video decoder to create a digital video data stream output, which is transferred to the Xilinx XC2VP4 FPGA for handling. Generation of S-Video output starts with a digital video stream coming from the FPGA, written into the ADV7321A video encoder to product the Y/C analog outputs, which are conditioned and output to the J20 S-Video connector.
  • Page 23 S-Video Input and Output Figure 3-2: S-Video, Composite, and Component Input and Output Signal Conditioning Circuit www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...

  • Page 24: Adv7403 S-Video Input

    U and V between them carry the color information. Composite video input and output is supported on the VIODC card through RCA type jack J18, this dual RCA jack has the composite video input on X1 and output on X2 and are color coded yellow.

  • Page 25: Composite Video Input

    J18 X2. ADV7321A Composite Video Output The XC2VP4 Xilinx FPGA provides both the digital video data stream and the configuration to the ADV7321A. Configuration of the ADV7321A defines the interface connections and active pins for the connection from the XC2VP4 and to the ADV7321A.

  • Page 26: Component Video Input And Output

    110 MHz ADCs, with 12-bit resolution, supporting HDTV for 525p, 625p, 720p and 1080i as well as RGB graphics support from VGA to SXGA at 60 frames per second. The digitized video output is connected directly to the Xilinx FPGA through a digital data, video timing control and I C control busses.

  • Page 27: Component Video Output

    Figure 3-4: Connections from ADV7403 Video Decoder to XC2VP4 FGPA Component Video Output Compliant digital video streams are feed into the ADV7321 device by the Xilinx XC2VP4 FPGA, where it is converted to analog RGB or YPrPb using 12-bit DACs. The ADV7321 device, from Analog Devices, produces fully compliant SD/HD analog output signals, which are then conditioned and drive the RCA type jacks.

  • Page 28: Analog Output Signal Conditioning

    ENABLE SDTI line count mode 0xb3 0xfe SDTI ADC sw1 0xc3 0x54 [7:4]=adc1 [3:0]=adc0 ADC sw2 0xc4 0x86 [7]=sw_en, [6]=SOG [3:0]=adc2 0x0e 0x80 Startup sequence 0x52 0x46 0x54 0x00 0x0e 0x00 www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...
  • Page 29 0x01 Mode Video 0x06 0x0c [2:0] =PRIM_MODE Standard Enable 0x1D 0x47 [3:0]= VID_STD XTAL ADC power 0x3a 0x21 Latch clock and PLL Bias Control 0x3b 0x80 External Bias Enable' www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...

  • Page 30: Adv7321A Configuration Modes

    0x00 0x0e 0x00 Notes: 1. The ADC sw1 and sw2 are unique to the VIODC input configuration. Refer to the ADV7403 data sheet for other video configurations. ADV7321A Configuration Modes Table 3-2, details the parameters setting for the internal registers of the ADV7321A Video Encoder device for each of the supported video standards.
  • Page 31 Power Mode 0x00 0xFE Input Mode 0x01 0x20 Mode 0x02 0x30 HD Mode 0x10 0x00 Reg 1 HD Mode 0x11 0x01 Reg 2 HD Mode 0x13 0x04 Reg 4 www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...
  • Page 32 Reg 1 HD Mode 0x11 0x01 Reg 2 HD Mode 0x13 0x04 Reg 4 HD Mode 0x15 0x00 Reg 6 Refer to the ADV7321A data sheet for other video configurations. www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...

  • Page 33: Chapter 4: Dvi/Vga Input Interface

    This includes analog VGA formats and digital DVI up to 1600x1200 at 60 Hz. DVI Connectivity on VIODC The DVI/VGA input portion of the video input and output daughter card (VIODC) has two connectors. The first is a traditional HD15 as used by all older analog video cards and monitors.

  • Page 34: Dvi Interface

    640 x 480 at 60 Hz analog. To allow higher resolutions or to enable the DVI interface, the receiver must report that it is capable of these modes. To support this, VIODC includes EEPROMs on the DDC (separate for each connector) that can be programmed with this structure.

  • Page 35: Vga Standard Overview

    VSYNC resets the beam to the top of the screen, and when released it slowly sweeps downward. The monitor locks its vertical and horizontal sweep rates to the VSYNC and HSYNC frequencies, respectively. HSYNC VSYNC Video Data HSYNC Figure 4-3: Synchronization Signaling www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...

  • Page 36: Setting The Pll And Phase

    Figure 4-5 example, the multiplication value is 1+1+2+12 = 16. The PLL in the AD9887A is free-running, so ADC samples occur during blanking (gray arrows) as well as active video www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...

  • Page 37: Setting Black Levels

    The single pixel more would be desirable to reduce the number of signals, but the AD9887A has a max DATACK frequency of 140 MHz, so for pixel rates greater than 140 MHz, the bus has to be operated in dual pixel mode. www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com...

  • Page 38: Dvi Input

    Default phase = T/2 Clamp Placement 0x05 0x24 36 cycles after HSYNC Clamp Duration 0x06 0x24 36 cycles in duration HSOUT Pulse width 0x07 0x80 128 cycles in HSYNC www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...
  • Page 39 PLL Div LSB 0x02 0xF0 VCO/CPMP 0x03 0xD4 VCORNGE = 10, CURRENT = 101 Phase Adjust 0x04 0x80 Default phase = T/2 Clamp Placement 0x05 0x78 120 cycles after HSYNC www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...

  • Page 40: Dvi

    References to VGA, DVI Standards Official VGA standards are available for purchase from the Video Electronics Standards Association at: http://www.vesa.org. DVI specifications are freely available from the Digital Display Working Group at http://www.ddwg.org. www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...

  • Page 41: Chapter 5: Dvi/Vga Output Interface

    DVI/VGA Output Interface Overview The VIODC supports both digital and analog outputs over the DVI output connector. The interface supports standards up to UXGA (165 MHz pixel clock). By connecting a VGA to the DVI adapter to the DVI output connector, VGA output is also supported.

  • Page 42: Tpf410 I2C Configuration

    0x70/0x71. Table 5-1: Configuration Modes for TPF410 I2C Video Encoder Chip Register Name Register Address Register Value Description ctl_1_mode 0x08 0x3F [5]=vsyc_enable [4]=hsyc_enable [3]=dontcare [2]=24-bit operation [1]=posedge [0]=powerup www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...

  • Page 43: Chapter 6: Sdi Interface

    Cook Technologies SDV board). This chapter demonstrates the use of the SDI interfaces on the VIODC in both SD-SDI and HD-SDI modes and provides a basic demonstration of how to implement the SDI receiver and transmitter interface. The code provided can easily be modified to send the video received by the SDI receiver to different video interfaces or to the ML402 board for further processing.

  • Page 44: Sdi Receiver

    SDI transmitter due to higher jitter on the reference clock. The receiver section requires 108 MHz and cannot get by with 54 MHz. However, jitter on the RocketIO reference clock is not as important for the receiver. www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card...

  • Page 45: Picoblaze Controller For The Adv7321B Video Encoder

    EDH packets compliant with SMPTE RP 165. Finally, the video is sent to the ADV7321B video encoder and output from the VIODC as analog composite video. The data ready signal from the data recovery unit, used as a clock enable to the SDI receiver logic, is output to the ADV7321B encoder as a 27 MHz video clock for the SD video.
  • Page 46 A ChipScope™ Pro VIO module is instantiated in the design to provide the user interface to this debugging capability. With the demo design loaded in the Virtex-II Pro FPGA on the VIODC, the debugger can be activated by starting ChipScope Pro and loading the adv_debugger.cpj ChipScope project.
  • Page 47 SD mode 6 0x48 0x10 10-bit input SD timing 0 0x4A 0x08 SD timing mode 0 and blank disabled SD Fsc 0 0x4C 0xCB SD Fsc 1 0x4D 0x8A www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...

  • Page 48: Sdi Transmitter

    The video pattern and format is selected either by the DIP switches on the VIODC or by the ML402 board. The HD pattern generator also produces an 11-bit line number value. The line number is inserted into the video stream after each End of Active Video (EAV) by the line number insertion logic.

  • Page 49: References

    Xilinx application note XAPP683: Multi-Rate HD/SD-SDI Transmitter Using Virtex-II Pro RocketIO Multi-Gigabit Transceivers. Xilinx application note XAPP684: Multi-Rate HD/SD-SDI Receiver Using Virtex-II Pro RocketIO Multi-Gigabit Transceivers. Xilinx application note XAPP579: Multi-Rate SDI integration Examples for the Serial Digital Video Demonstration Board. www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com...
  • Page 50 Chapter 6: SDI Interface www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...

  • Page 51: Chapter 7: Image Sensor Camera Interface

    It features low noise and very high dynamic range. The interface is implemented using LVDS signaling over standard Cat-6 Ethernet cables. See Figure 7-1. Note: The LVDS camera interface is not compatible with Ethernet. VIODC Cat 6 Cable RJ45 Connect ug235_ch6_01_120805 Figure 7-1: LVDS Camera Interface...
  • Page 52 This requires the FPGA receiver to have the ability to adjust or skew the camera clock phase to clock in valid camera data. This is shown in Figure 7-1. www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...

  • Page 53: Chapter 8: Attaching The Viodc To The Ml40X Development Board

    Attaching the VIODC to the ML40x Development Board The VIODC can be used in a standalone mode or mounted to a ML401, ML402, or ML403 development board. When the VIODC board is mounted on the ML40x, several jumpers are required to be configured properly for correct operation. The required jumper positions...
  • Page 54 Chapter 8: Attaching the VIODC to the ML40x Development Board TDO EXP Pin(2,3)= Back=VIODC+ML402 Pin(1, 2 )=Front=ML402 Pin(2,3)= Back =VIODC+ML402 Pin(1, 2 )=Front=ML402 ug235_ch8_011606 Figure 8-1: Configuration Jumper Locations on the ML40x Bottom, Configured for VIODC Mounted to an ML402 Board...

  • Page 55: Schematic And Data Sheet Links

    Appendix A Reference Information Schematic and Data Sheet Links Schematics VIODC schematic VIODC ML402 schematic ML402 Table A-1: VIODC ICs Manufacturer Part Number Function Web Page Data Sheet ANALOG_DEVICES AD9887AKS-170 DVI Receiver A&D AD9887A AD9887A ANALOG_DEVICES ADV7321AKST Video Encoder ADV7321A...

  • Page 56: Viobus Pinouts

    Appendix A: Reference Information VIOBUS Pinouts Table A-2: VIOBUS Signals XGI Header Connections VIOBUS VIOBUS ML402 VIODC Single-Ended Mode Differential Mode XC4VSX35 XC2VP4 Header Signal Name Signal Name vio_up0 vio_up_lvds0_N hdr2 vio_up1 vio_up_lvds0_P hdr2 AA18 vio_up2 vio_up_lvds1_N hdr2 vio_up3 vio_up_lvds1_P...
  • Page 57 VIOBUS Pinouts Table A-2: VIOBUS Signals XGI Header Connections (Continued) VIOBUS VIOBUS ML402 VIODC Single-Ended Mode Differential Mode XC4VSX35 XC2VP4 Header Signal Name Signal Name vio_dn13 vio_dn_lvds6_P hdr2 AF19 vio_dn14 vio_dn_lvds7_N hdr2 AE18 vio_dn15 vio_dn_lvds7_P hdr2 AF18 vio_up16 vio_up0 hdr1...
  • Page 58 Appendix A: Reference Information Table A-2: VIOBUS Signals XGI Header Connections (Continued) VIOBUS VIOBUS ML402 VIODC Single-Ended Mode Differential Mode XC4VSX35 XC2VP4 Header Signal Name Signal Name vio_i2c_sda_dn vio_i2c_sda_dn hdr1 AB21 AA14 vio_i2c_sda_up vio_i2c_sda_up hdr1 AD22 vio_up_clk_lvds_N vio_up_clk_lvds_N hdr1 AE24...
  • Page 59 HDR1_30 vio_dn22 vio_dn6 IO_L15N_7_AD23 AD23 HDR1_6 vio_dn23 vio_dn7 IO_L9N_CC_LC_7_AC26 AC26 HDR1_34 vio_dn24 vio_dn8 IO_L11N_7_AD26 AD26 HDR1_18 vio_dn25 vio_dn9 IO_L13P_7_AC22 AC22 HDR1_16 vio_dn_clk_ena vio_dn_clk_ena IO_L1N_7_V22 HDR1_54 vio_reset vio_reset IO_L1P_7_V21 HDR1_56 www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...
  • Page 60 IO_L15P_7_AD22 AD22 HDR1_8 vio_up_clk_lvds_N vio_up_clk_lvds_N IO_L22N_7_AE24 AE24 HDR1_62 vio_up_clk_lvds_P vio_up_clk_lvds_P IO_L22P_7_AF24 AF24 HDR1_64 Table A-4: VIOBUS VIODC FPGA Connections VIOBUS Single- VIOBUS VIODC VIODC Schematic Ended Mode Differential Mode XCV2P4 FPGA Signal Name Signal Name Signal Name Pin Name vio_up0...
  • Page 61 VIOBUS Pinouts Table A-4: VIOBUS VIODC FPGA Connections (Continued) VIOBUS Single- VIOBUS VIODC VIODC Schematic Ended Mode Differential Mode XCV2P4 FPGA Signal Name Signal Name Signal Name Pin Name vio_dn1 vio_dn_lvds0_P IO_L68P_0_C15 V4_IOB_L32_P vio_dn2 vio_dn_lvds1_N IO_L09N_0_G18 V4_IOB_L23_N vio_dn3 vio_dn_lvds1_P IO_L09P_0/VREF_0_F18...
  • Page 62 Appendix A: Reference Information Table A-4: VIOBUS VIODC FPGA Connections (Continued) VIOBUS Single- VIOBUS VIODC VIODC Schematic Ended Mode Differential Mode XCV2P4 FPGA Signal Name Signal Name Signal Name Pin Name vio_dn21 vio_dn5 IO_L07N_5/VREF_5_AD19 AD19 V4_IOB_L7_N vio_dn22 vio_dn6 IO_L67N_5_AB15 AB15...

  • Page 63: Appendix B: Vsk I/O Connector Location Pictures

    VSK I/O Connector Location Pictures VIODC Connectors VIODC VGA In LVDS VIODC ML402 Power Camera ML402 Ethernet JTAG Switch VGA Out ML402 Connector 5V Power Audio Input Figure B-1: VIODC Rear View www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...
  • Page 64 Appendix B: VSK I/O Connector Location Pictures VIODC VIODC ML402 ML402 DVI In DVI/VGA Out JTAG RS-232 Figure B-2: VIODC Left Side View www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...
  • Page 65 Composite VIODC VIODC VIODC VIODC VIODC Y Out VIODC S-Video Composite S-Video VIODC Pb Out Pr Out Y In Pr In Pb In Figure B-3: VIODC Right Side View www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...
  • Page 66 Appendix B: VSK I/O Connector Location Pictures LVDS Camera LVDS Camera HOST Port Figure B-4: LVDS Camera www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...
  • Page 67 ML402 Board ML402 Board Figure B-5: ML402 Board www.BDTIC.com/XILINX Video Input/Output Daughter Card www.xilinx.com UG235 (v1.2.1) October 31, 2007...
  • Page 68 Appendix B: VSK I/O Connector Location Pictures Figure B-6: ML402 Evaluation Platform www.BDTIC.com/XILINX www.xilinx.com Video Input/Output Daughter Card UG235 (v1.2.1) October 31, 2007...

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