Xilinx VCU1287 User Manual page 29

User LEDs (Active-High)
DS19 through DS26 (callout 24,
to user I/O pins on the FPGA as shown in
status or for other purposes.
Table 3-11: User LEDs
Pin Function
BD14 User LED
BF15 User LED
BE15 User LED
BE13 User LED
BD13 User LED
BC14 User LED
BB15 User LED
BB14 User LED
User DIP Switches (Active-High) and I/O Header
The DIP switch SW3 (callout 28,
connect to user I/O pins on the FPGA as shown in
control pins or for other purposes. The eight I/Os also map to a test header J95 (callout 29,
Figure 2-1) providing external access for these pins. The I/O pins can be connected to the
onboard system controller as additional GPIO between the two devices.
Install J7 to connect the user DIP switches to the system controller.
IMPORTANT:
Table 3-12: User DIP Switches
FPGA(U1)
Pin Function
AP13 User switch
AU16 User switch
AU14 User switch
AV14 User switch
AR13 User switch
AV16 User switch
AW16 User switch
AW15 User switch
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Figure
FPGA(U1)
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Figure
Direction IOSTANDARD
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
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Chapter 3:
2-1) are eight active-High LEDs that are connected
Table 3-11. These LEDs can be used to indicate
Schematic Net
Name
IOSTANDARD
LVCMOS18 APP_LED1
LVCMOS18 APP_LED2
LVCMOS18 APP_LED3
LVCMOS18 APP_LED4
LVCMOS18 APP_LED5
LVCMOS18 APP_LED6
LVCMOS18 APP_LED7
LVCMOS18 APP_LED8
2-1) provides a set of eight active-High switches that
Table 3-12. These pins can be used to set
DIP Switch
Schematic Net
Reference
Name
Designator
USER_SW1
USER_SW2
USER_SW3
USER_SW4
SW3
USER_SW5
USER_SW6
USER_SW7
USER_SW8
Board Component Descriptions
Reference
Designator
DS19
DS20
DS21
DS25
DS24
DS23
DS22
DS26
J95 Test Device(U38)
Header Pin Pin
1 F12
3 E13
5 E11
7 E12
9 F13
11 F14
13 G15
15 F15
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