Xilinx VCU1287 User Manual page 28

SuperClock-2 Module
The SuperClock-2 module (callout 11,
connector (J36) and provides a programmable, low-noise and low-jitter clock source for the
VCU1287 board. The clock module maps to FPGA I/O by way of 14 control pins, 2 LVDS
pairs, 1 regional clock pair, and 1 reset pin.
SuperClock-2 module interface. The VCU1287 board supplies UTIL_5V0, UTIL_3V3, UTIL_2V5
and VCCO_HP input power to the
Table 3-10: SuperClock-2 FPGA I/O Mapping
FPGA(U1)
Pin Function
L13 Clock recovery
K13 Clock recovery
J33 Clock recovery
H33 Clock recovery
G26 Regional clock
G27 Regional clock
B30 Control I/O
A30 Control I/O
B29 Control I/O
A29 Control I/O
A27 Control I/O
A28 Control I/O
E30 Control I/O
D30 Control I/O
D29 CONTROL I/O
C29 CONTROL I/O
C27 CONTROL I/O
B27 CONTROL I/O
C28 CM_RESET
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Figure
Table 3-10
Direction IOSTANDARD
Input LVDS
Input LVDS
Input LVDS
Input LVDS
Input LVDS
Input LVDS
Output LVCMOS
Output LVCMOS
Output LVCMOS
Input LVCMOS
Output LVCMOS
Output LVCMOS
Output LVCMOS
Output LVCMOS
Output LVCMOS
Output LVCMOS
Output LVCMOS
Output LVCMOS
Output LVCMOS
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Chapter 3: Board Component Descriptions
2-1) connects to the clock module interface
Table 3-10 shows the FPGA I/O mapping for the
clock module interface.
Schematic Net
Name
Pin
CM_LVDS1_P 1
CM_LVDS1_N 3
CM_LVDS2_P 9
CM_LVDS2_N 11
CM_GCLK_P 25
CM_GCLK_N 27
CM_H_DEC 67
CM_H_INC 69
CM_FS_ALIGN 71
CM_H_LOL 79
CM_H_INT_ALRM 81
CM_C1B 83
CM_C2B 85
CM_C3B 87
CM_C1A 89
CM_C2A 91
CM_H_CS0_C3A 95
CM_H_CS1_C4A 97
CM_RST 66
J36 Pin
Function Direction
Clock recovery Output
Clock recovery Output
Clock recovery Output
Clock recovery Output
Global clock Output
Global clock Output
DEC Input
INC Input
ALIGN Input
LOL Output
INT_ALRM Input
C1B Input
C2B Input
C3B Input
C1A Input
C2A Input
CS0_C3A Input
CS1_C4A Input
RESET_B Input
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