Xilinx VCU1287 User Manual page 31

MGT Transceivers and Reference Clocks
The VCU1287 board provides access to all GTY and GTH transceiver and reference clock pins
on the XCVU095 FPGA as shown in
eight sets of four TX-RX lanes, referred to as a GTY Quads (Q124 - Q131) on the right side
of the board and eight TX-RX lanes, referred to as GTH Quads (Q224 - Q231) on the left side
of the board.
Figure 3-11
IMPORTANT:
Quad 132, Quad 232, and Quad 233 are not available on the XCVU095 FPGA device density.
X-Ref Target - Figure 3-11
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Figure 3-11. The MGT transceivers are grouped into
is for reference only and might not reflect the current revision of the board.
Figure 3-11: MGT Quad Locations
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Chapter 3: Board Component Descriptions
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