Xilinx VCU1287 User Manual page 77

Characterization board
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set_property PACKAGE_PIN W37
set_property PACKAGE_PIN P38
set_property PACKAGE_PIN P39
set_property PACKAGE_PIN P43
set_property PACKAGE_PIN P44
set_property PACKAGE_PIN R40
set_property PACKAGE_PIN R41
set_property PACKAGE_PIN R45
set_property PACKAGE_PIN R46
set_property PACKAGE_PIN T38
set_property PACKAGE_PIN T39
set_property PACKAGE_PIN T43
set_property PACKAGE_PIN T44
set_property PACKAGE_PIN U40
set_property PACKAGE_PIN U41
set_property PACKAGE_PIN U45
set_property PACKAGE_PIN U46
set_property PACKAGE_PIN N36
set_property PACKAGE_PIN N37
set_property PACKAGE_PIN R36
set_property PACKAGE_PIN R37
set_property PACKAGE_PIN J40
set_property PACKAGE_PIN J41
set_property PACKAGE_PIN K43
set_property PACKAGE_PIN K44
set_property PACKAGE_PIN L40
set_property PACKAGE_PIN L41
set_property PACKAGE_PIN L45
set_property PACKAGE_PIN L46
set_property PACKAGE_PIN M38
set_property PACKAGE_PIN M39
set_property PACKAGE_PIN M43
set_property PACKAGE_PIN M44
set_property PACKAGE_PIN N40
set_property PACKAGE_PIN N41
set_property PACKAGE_PIN N45
set_property PACKAGE_PIN N46
set_property PACKAGE_PIN AV11
set_property PACKAGE_PIN AV10
set_property PACKAGE_PIN AW9
set_property PACKAGE_PIN AW8
set_property PACKAGE_PIN AV7
set_property PACKAGE_PIN AV6
set_property PACKAGE_PIN AV2
set_property PACKAGE_PIN AV1
set_property PACKAGE_PIN BB5
set_property PACKAGE_PIN BB4
set_property PACKAGE_PIN AW4
set_property PACKAGE_PIN AW3
set_property PACKAGE_PIN BD5
set_property PACKAGE_PIN BD4
set_property PACKAGE_PIN BA2
set_property PACKAGE_PIN BA1
set_property PACKAGE_PIN BF5
set_property PACKAGE_PIN BF4
set_property PACKAGE_PIN BC2
set_property PACKAGE_PIN BC1
set_property PACKAGE_PIN AP11
set_property PACKAGE_PIN AP10
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Appendix Appendix C:
[get_ports "130_REFCLK0_N"]
[get_ports "130_TX3_P"]
[get_ports "130_TX3_N"]
[get_ports "130_RX3_P"]
[get_ports "130_RX3_N"]
[get_ports "130_TX2_P"]
[get_ports "130_TX2_N"]
[get_ports "130_RX2_P"]
[get_ports "130_RX2_N"]
[get_ports "130_TX1_P"]
[get_ports "130_TX1_N"]
[get_ports "130_RX1_P"]
[get_ports "130_RX1_N"]
[get_ports "130_TX0_P"]
[get_ports "130_TX0_N"]
[get_ports "130_RX0_P"]
[get_ports "130_RX0_N"]
[get_ports "131_REFCLK1_P"]
[get_ports "131_REFCLK1_N"]
[get_ports "131_REFCLK0_P"]
[get_ports "131_REFCLK0_N"]
[get_ports "131_TX3_P"]
[get_ports "131_TX3_N"]
[get_ports "131_RX3_P"]
[get_ports "131_RX3_N"]
[get_ports "131_TX2_P"]
[get_ports "131_TX2_N"]
[get_ports "131_RX2_P"]
[get_ports "131_RX2_N"]
[get_ports "131_TX1_P"]
[get_ports "131_TX1_N"]
[get_ports "131_RX1_P"]
[get_ports "131_RX1_N"]
[get_ports "131_TX0_P"]
[get_ports "131_TX0_N"]
[get_ports "131_RX0_P"]
[get_ports "131_RX0_N"]
[get_ports "224_REFCLK1_P"]
[get_ports "224_REFCLK1_N"]
[get_ports "224_REFCLK0_P"]
[get_ports "224_REFCLK0_N"]
[get_ports "224_TX3_P"]
[get_ports "224_TX3_N"]
[get_ports "224_RX3_P"]
[get_ports "224_RX3_N"]
[get_ports "224_TX2_P"]
[get_ports "224_TX2_N"]
[get_ports "224_RX2_P"]
[get_ports "224_RX2_N"]
[get_ports "224_TX1_P"]
[get_ports "224_TX1_N"]
[get_ports "224_RX1_P"]
[get_ports "224_RX1_N"]
[get_ports "224_TX0_P"]
[get_ports "224_TX0_N"]
[get_ports "224_RX0_P"]
[get_ports "224_RX0_N"]
[get_ports "225_REFCLK1_P"]
[get_ports "225_REFCLK1_N"]
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