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#SYSTEM CLOCK
set_property PACKAGE_PIN AW14
set_property IOSTANDARD
set_property PACKAGE_PIN AW13
set_property IOSTANDARD
#PMBUS
set_property PACKAGE_PIN AY12
set_property IOSTANDARD
set_property PACKAGE_PIN BD16
set_property IOSTANDARD
set_property PACKAGE_PIN BE16
set_property IOSTANDARD
set_property PACKAGE_PIN AU25
set_property IOSTANDARD
set_property PACKAGE_PIN AM26
set_property IOSTANDARD
set_property PACKAGE_PIN AN26
set_property IOSTANDARD
set_property PACKAGE_PIN AL25
set_property IOSTANDARD
set_property PACKAGE_PIN AM25
set_property IOSTANDARD
set_property PACKAGE_PIN AL15
set_property IOSTANDARD
set_property PACKAGE_PIN AN13
set_property IOSTANDARD
set_property PACKAGE_PIN AP15
set_property IOSTANDARD
set_property PACKAGE_PIN AP14
set_property IOSTANDARD
#UART
set_property PACKAGE_PIN BF14
set_property IOSTANDARD
set_property PACKAGE_PIN BF13
set_property IOSTANDARD
set_property PACKAGE_PIN BB12
set_property IOSTANDARD
set_property PACKAGE_PIN BA12
set_property IOSTANDARD
#USB_GPIOs
set_property PACKAGE_PIN AY15
set_property IOSTANDARD
set_property PACKAGE_PIN AV13
set_property IOSTANDARD
set_property PACKAGE_PIN AR15
set_property IOSTANDARD
set_property PACKAGE_PIN AR16
set_property IOSTANDARD
#MGTs
set_property PACKAGE_PIN AY38
set_property PACKAGE_PIN AY39
set_property PACKAGE_PIN BA40
set_property PACKAGE_PIN BA41
set_property PACKAGE_PIN AW40
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Appendix Appendix C:
[get_ports "LVDS_OSC_P"]
LVDS
[get_ports "LVDS_OSC_P"]
[get_ports "LVDS_OSC_N"]
LVDS
[get_ports "LVDS_OSC_N"]
[get_ports "DUT_PMBUS_ALERT"]
LVCMOS18 [get_ports "DUT_PMBUS_ALERT"]
[get_ports "DUT_PMBUS_CLK"]
LVCMOS18 [get_ports "DUT_PMBUS_CLK"]
[get_ports "DUT_PMBUS_DATA"]
LVCMOS18 [get_ports "DUT_PMBUS_DATA"]
[get_ports "DUT_SMAP_CSI_B"]
LVCMOS18 [get_ports "DUT_SMAP_CSI_B"]
[get_ports "DUT_SMAP_D4"]
LVCMOS18 [get_ports "DUT_SMAP_D4"]
[get_ports "DUT_SMAP_D5"]
LVCMOS18 [get_ports "DUT_SMAP_D5"]
[get_ports "DUT_SMAP_D6"]
LVCMOS18 [get_ports "DUT_SMAP_D6"]
[get_ports "DUT_SMAP_D7"]
LVCMOS18 [get_ports "DUT_SMAP_D7"]
[get_ports "DUT_FREQ_CLK"]
LVCMOS18 [get_ports "DUT_FREQ_CLK"]
[get_ports "DUT_FREQ_DATA"]
LVCMOS18 [get_ports "DUT_FREQ_DATA"]
[get_ports "DUT_FREQ_BSY"]
LVCMOS18 [get_ports "DUT_FREQ_BSY"]
[get_ports "DUT_FREQ_RDY"]
LVCMOS18 [get_ports "DUT_FREQ_RDY"]
[get_ports "UART_TXD_O"]
LVCMOS18 [get_ports "UART_TXD_O"]
[get_ports "UART_RXD_I"]
LVCMOS18 [get_ports "UART_RXD_I"]
[get_ports "UART_RTS_O_B"]
LVCMOS18 [get_ports "UART_RTS_O_B"]
[get_ports "UART_CTS_I_B"]
LVCMOS18 [get_ports "UART_CTS_I_B"]
[get_ports "UART_GPIO_0"]
LVCMOS18 [get_ports "UART_GPIO_0"]
[get_ports "UART_GPIO_1"]
LVCMOS18 [get_ports "UART_GPIO_1"]
[get_ports "UART_GPIO_2"]
LVCMOS18 [get_ports "UART_GPIO_2"]
[get_ports "UART_GPIO_3"]
LVCMOS18 [get_ports "UART_GPIO_3"]
[get_ports "124_REFCLK1_P"]
[get_ports "124_REFCLK1_N"]
[get_ports "124_REFCLK0_P"]
[get_ports "124_REFCLK0_N"]
[get_ports "124_TX3_P"]
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Master Constraints File Listing
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