Xilinx VCU1287 User Manual page 76

Characterization board
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set_property PACKAGE_PIN AF38
set_property PACKAGE_PIN AF39
set_property PACKAGE_PIN AF43
set_property PACKAGE_PIN AF44
set_property PACKAGE_PIN AG40
set_property PACKAGE_PIN AG41
set_property PACKAGE_PIN AG45
set_property PACKAGE_PIN AG46
set_property PACKAGE_PIN AH38
set_property PACKAGE_PIN AH39
set_property PACKAGE_PIN AH43
set_property PACKAGE_PIN AH44
set_property PACKAGE_PIN AJ40
set_property PACKAGE_PIN AJ41
set_property PACKAGE_PIN AJ45
set_property PACKAGE_PIN AJ46
set_property PACKAGE_PIN AE36
set_property PACKAGE_PIN AE37
set_property PACKAGE_PIN AG36
set_property PACKAGE_PIN AG37
set_property PACKAGE_PIN AB38
set_property PACKAGE_PIN AB39
set_property PACKAGE_PIN AB43
set_property PACKAGE_PIN AB44
set_property PACKAGE_PIN AC40
set_property PACKAGE_PIN AC41
set_property PACKAGE_PIN AC45
set_property PACKAGE_PIN AC46
set_property PACKAGE_PIN AD38
set_property PACKAGE_PIN AD39
set_property PACKAGE_PIN AD43
set_property PACKAGE_PIN AD44
set_property PACKAGE_PIN AE40
set_property PACKAGE_PIN AE41
set_property PACKAGE_PIN AE45
set_property PACKAGE_PIN AE46
set_property PACKAGE_PIN AA36
set_property PACKAGE_PIN AA37
set_property PACKAGE_PIN AC36
set_property PACKAGE_PIN AC37
set_property PACKAGE_PIN V38
set_property PACKAGE_PIN V39
set_property PACKAGE_PIN V43
set_property PACKAGE_PIN V44
set_property PACKAGE_PIN W40
set_property PACKAGE_PIN W41
set_property PACKAGE_PIN W45
set_property PACKAGE_PIN W46
set_property PACKAGE_PIN Y38
set_property PACKAGE_PIN Y39
set_property PACKAGE_PIN Y43
set_property PACKAGE_PIN Y44
set_property PACKAGE_PIN AA40
set_property PACKAGE_PIN AA41
set_property PACKAGE_PIN AA45
set_property PACKAGE_PIN AA46
set_property PACKAGE_PIN U36
set_property PACKAGE_PIN U37
set_property PACKAGE_PIN W36
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Appendix Appendix C:
[get_ports "127_TX3_P"]
[get_ports "127_TX3_N"]
[get_ports "127_RX3_P"]
[get_ports "127_RX3_N"]
[get_ports "127_TX2_P"]
[get_ports "127_TX2_N"]
[get_ports "127_RX2_P"]
[get_ports "127_RX2_N"]
[get_ports "127_TX1_P"]
[get_ports "127_TX1_N"]
[get_ports "127_RX1_P"]
[get_ports "127_RX1_N"]
[get_ports "127_TX0_P"]
[get_ports "127_TX0_N"]
[get_ports "127_RX0_P"]
[get_ports "127_RX0_N"]
[get_ports "128_REFCLK1_P"]
[get_ports "128_REFCLK1_N"]
[get_ports "128_REFCLK0_P"]
[get_ports "128_REFCLK0_N"]
[get_ports "128_TX3_P"]
[get_ports "128_TX3_N"]
[get_ports "128_RX3_P"]
[get_ports "128_RX3_N"]
[get_ports "128_TX2_P"]
[get_ports "128_TX2_N"]
[get_ports "128_RX2_P"]
[get_ports "128_RX2_N"]
[get_ports "128_TX1_P"]
[get_ports "128_TX1_N"]
[get_ports "128_RX1_P"]
[get_ports "128_RX1_N"]
[get_ports "128_TX0_P"]
[get_ports "128_TX0_N"]
[get_ports "128_RX0_P"]
[get_ports "128_RX0_N"]
[get_ports "129_REFCLK1_P"]
[get_ports "129_REFCLK1_N"]
[get_ports "129_REFCLK0_P"]
[get_ports "129_REFCLK0_N"]
[get_ports "129_TX3_P"]
[get_ports "129_TX3_N"]
[get_ports "129_RX3_P"]
[get_ports "129_RX3_N"]
[get_ports "129_TX2_P"]
[get_ports "129_TX2_N"]
[get_ports "129_RX2_P"]
[get_ports "129_RX2_N"]
[get_ports "129_TX1_P"]
[get_ports "129_TX1_N"]
[get_ports "129_RX1_P"]
[get_ports "129_RX1_N"]
[get_ports "129_TX0_P"]
[get_ports "129_TX0_N"]
[get_ports "129_RX0_P"]
[get_ports "129_RX0_N"]
[get_ports "130_REFCLK1_P"]
[get_ports "130_REFCLK1_N"]
[get_ports "130_REFCLK0_P"]
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