Xilinx VCU1287 User Manual page 26

The connections of these signals between the FPGA and the CP2105 are listed in
Table 3-6: FPGA to UART Connection
FPGA(U1)
Pin Function
BA12 RTS
BB12 CTS
BF13 TX
BF14 RX
The bridge device also provides as many as four GPIO signals that can be defined for status
and control information
Table 3-7: CP2105 USB-to-UART Bridge User GPIO
FPGA(U1)
Function
Pin
AY15 SelectIO
AV13 SelectIO
AR15 SelectIO
AR16 SelectIO
The second port of the CP2105 USB-to-dual UART is connected to the onboard system
controller. See
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Direction IOSTANDARD
Output LVCMOS18
Input LVCMOS18
Output LVCMOS18
Input LVCMOS18
(Table 3-7).
Direction IOSTANDARD
IN/OUT LVCMOS18
IN/OUT LVCMOS18
IN/OUT LVCMOS18
IN/OUT LVCMOS18
Appendix D, System Controller.
www.xilinx.com
Chapter 3: Board Component Descriptions
Schematic Net
Name
Pin
UART_CTS_I_B 18
UART_RTS_O_B 19
UART_RXD_I 20
UART_TXD_O 21
Schematic Net
Name
Pin
UART_GPIO_0 24
UART_GPIO_1 23
UART_GPIO_2 22
UART_GPIO_3 15
Table 3-6.
Device(U32)
Function Direction
CTS Input
RTS Output
RXD Input
TXD Output
Device(U32)
Direction
Function
GPIO IN/OUT
GPIO IN/OUT
GPIO IN/OUT
GPIO IN/OUT
26
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