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Copyright © 2018, Juniper Networks, Inc.
Figure 5: Clock and Data Paths with Transparent Phase-Correction FIFO
Buffers
Transparent Circuit
DTE
Pin
2
SD
24
TT
4
RTS
20
DTR
FIFO
3
RD
17
RT
5
CTS
6
DSR
Like in TRANS encoding, you can use the 16 bit phase correction FIFO in TRANS 8 encoding
to accommodate the problems that can be caused by the high latency in the circuit
whether or not the remote DCE device can accept TT input or not.
When the customer DCE device can support the TT signal returned by the DTE, the phase
correction FIFO is not needed. The DCE transmit clock (ST) is sampled and carried
downstream to the DTE, where it is used to generate the upstream data that is sent back
to the customer DCE. This clock data is also sent as the DTE transmit clock (TT) to travel
along with the data in phase. When these signals get back to the customer DCE device,
they are still in phase (same delay through the network), so the customer DCE can use
the TT signal to recover the transmit data on the SD lead.
Consider a scenario in which the customer's upstream DCE does not use the TT signal
for capturing upstream data, and instead uses the ST clock. Here, due to the latency of
the ST clock traveling downstream and the time taken for the return trip of the data, it
is difficult to ensure error-free data transport. In such a scenario, you can use phase
correction FIFO to ensure error-free data transport.
The SD or TT clock and data signals get back to the upstream CTP device, where the
data is clocked into the FIFO using the TT clock, which is in phase. This data is clocked
out of the FIFO using the upstream ST clock, and the data is realigned to be in phase with
the ST clock.
Transparent Encoding Applications and Support Overview on page 12
How Basic Transparent Encoding Works on page 13
Using Send Timing (ST) Clocking for Higher Speed Circuits with Transparent Encoding
on page 16
Configuring Transparent Encoding for CTP Bundles (CTP Menu) on page 60
Configuring Transparent Encoding for CTP Bundles (CTPView) on page 58
Transparent Circuit
FIFO
Red = clock
Blue = data
Chapter 1: Overview of CTP Bundles
DCE
Pin
RD
3
RT
17
CTS
5
DSR
6
SD
2
TT
24
RTS
4
DTR
20
15
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