Configuring Adaptive Clocking For Ctp Bundles (Ctpview) - Juniper CTP Series Manual

Table 51: CTP Bundle Custom Clocking Settings in the CTP Menu (continued)
Field
TT (i/f bound i/f) clk sel
TX (i/f bound scc) clk sel

Configuring Adaptive Clocking for CTP Bundles (CTPView)

Copyright © 2018, Juniper Networks, Inc.
Function
Specifies the Transmit Timing clock on
the interface bound interface.
This parameter appears only if you have
configured the bundle as the DTE.
Specifies the clock used for the Transmit
Data path on the interface bound serial
communications controller (SCC).
The adaptive clocking configuration allows you to modify attributes that affect the
adaptive clocking algorithm. The default settings are acceptable for most applications.
We recommend that you change these settings only with the assistance of JTAC.
Before you begin:
Log in to the CTPView software at least at the Net_Admin level.
Connect the CTPView server to the CTP device for which you want to configure bundles.
To configure adaptive clocking for CTP bundles using CTPView:
In the side pane, select Bundle > Configuration.
1.
Run your mouse over the Display and Select an Existing Bundle bar.
2.
In the table of bundles, select the bundle that you want to modify.
3.
Chapter 2: Configuring CTP Bundles
Your Action
Select one:
ST (ext clk)—Send timing clock. The
interface clock signal from the DCE to
the DTE (CTP device).
DDS (synth)—Direct digital synthesizer
clock
RT (ext clk)—Receive timing clock.
Interface clock signal from the DCE to
the DTE (CTP device).
DIV (synth)—Divider clock generator.
Select one (the values that appear
depend on whether the bundle is
configured as the DCE or as the DTE):
OFF—No clock is used.
ST (ext clk)—Send timing clock. The
interface clock signal from the DCE to
the DTE (CTP device).
DDS (synth)—Direct digital synthesizer
clock
TT (ext clk)—Transmit timing clock.
The interface clock signal from the
DTE to the DCE (CTP device).
RT (ext clk)—Receive timing clock.
Interface clock signal from the DCE to
the DTE (CTP device).
DIV (synth)—Divider clock generator.
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