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Table 2-8
BAR Config / PCIe Window Sizes
BAR cfg
BAR0
0b0000
PCIe MMRs
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
2
2.4.2.5 I
C Boot Device Configuration
2
2.4.2.5.1 I
C Master Mode
2
In master mode, the I
C device configuration uses ten bits of device configuration instead of seven as used in other
boot modes. In this mode, the device will make the initial read of the I
The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.
2
Figure 2-7
I
C Master Mode Device Configuration Fields
12
11
Reserved
Speed
2
Table 2-9
I
C Master Mode Device Configuration Field Descriptions
Bit
Field
12
Reserved
11
Speed
10
Address
9
Reserved
8
Mode
7-3
Parameter Index
End of Table 2-9
Copyright 2012 Texas Instruments Incorporated
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32-Bit Address Translation
BAR1
BAR2
32
32
16
16
16
32
32
32
16
16
16
32
32
32
32
32
64
64
4
128
4
128
4
128
10
9
Address
Reserved
Description
Reserved
2
I
C data rate configuration
2
0 = I
C data rate set to approximately 20 kHz
2
1 = I
C fast mode. Data rate set to approximately 400 kHz (will not exceed)
2
I
C bus address configuration
2
2
0 = Boot from I
C EEPROM at I
C bus address 0x50
2
2
1 = Boot from I
C EEPROM at I
C bus address 0x51
Reserved
2
I
C operation mode
0 = Master mode
1 = Passive mode (see 2.4.2.5.2
Identifies the index of the configuration table initially read from the I
This value can range from 0 to 32.
Multicore Fixed and Floating-Point System-on-Chip
BAR3
BAR4
32
32
32
64
32
64
32
64
64
64
64
64
64
64
64
128
128
256
128
128
128
256
256
256
2
C EEPROM while the PLL is in bypass mode.
8
7
Mode
''I2C Passive
Mode'')
TMS320C6670
SPRS689D—March 2012
64-Bit Address Translation
BAR5
BAR2/3
Clone of BAR4
256
512
1024
2048
6
5
4
Parameter Index
2
C EEPROM.
Device Overview
BAR4/5
256
512
1024
2048
3
33
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