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Table 7-69
SPI Switching Characteristics (Part 2 of 2)
(See
Figure 7-38
and
Figure
7-39)
No.
6
toh(SPC-SIMO)
Output hold time, SPIx_SIMO valid after receive edge of SPIx_CLK except for
final bit. Polarity = 1 Phase = 1
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 0
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 0 Phase = 1
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 0
19
td(SCS-SPC)
Delay from SPIx_SCS\ active to first SPIx_CLK. Polarity = 1 Phase = 1
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0
Phase = 0
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 0
Phase = 1
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1
Phase = 0
20
td(SPC-SCS)
Delay from final SPIx_CLK edge to master deasserting SPIx_SCS\. Polarity = 1
Phase = 1
tw(SCSH)
Minimum inactive time on SPIx_SCS\ pin between two transfers when
SPIx_SCS\ is not held using the CSHOLD feature.
End of Table 7-69
1 P2=1/SYSCLK7
Copyright 2012 Texas Instruments Incorporated
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Multicore Fixed and Floating-Point System-on-Chip
Parameter
Additional SPI Master Timings — 4 Pin Mode with Chip Select Option
TMS320C6670 Peripheral Information and Electrical Specifications
TMS320C6670
SPRS689D—March 2012
Min
Max
0.5*tc - 2
2*P2 - 5
2*P2 + 5 ns
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
2*P2 - 5
2*P2 + 5 ns
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
1*P2 - 5
1*P2 + 5
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5
1*P2 - 5
1*P2 + 5
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5
2*P2 - 5
Unit
ns
ns
ns
ns
ns
ns
201
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