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TMS320C6670
Multicore Fixed and Floating-Point System-on-Chip
SPRS689D—March 2012
www.ti.com
Corrected RESET Electrical timing parameters (Page 126)
Removed RESETFULLz parameter from t4b timing description (Page 112)
Revision A
Updated the complete Power-up sequencing section. RESETFULLz must always de-assert after PORz (Page 110)
Updated the description of VARIANT bit field in JTAGID register (Page 73)
Added Setup and Hold times for RP1CLK and RP1CLK signals. (Page 213)
Corrected the size of TETBs for the 4 cores from 16k to 4k (Page 26)
Added RSV0A and RSV0B pins to the Terminal list table (Page 51)
Changed DDR3PLLCTL0 to DDR3PLLCTL and PAPLLCTL0 to PASSPLLCTL (Page 70)
Cleaned up power rail terminology and changed reference parameter in t2c description from t7 to t6 (Page 112)
Added a note on Level Interrupts and EOI values for various modules. (Page 155)
Corrected the address range for I2C MMRs (Page 196)
Corrected Extended Temp max to 100C from 105C (Page 13)
Added BWADJ field to DDR3PLLCTL (Page 143)
Added BWADJ field to PASSPLLCTL (Page 146)
220
Revision History
Copyright 2012 Texas Instruments Incorporated
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